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1. 发明授权

US5889395A Integrated low voltage regulator for high capacitive loads 失效
标题翻译：集成低压稳压器，用于高容性负载
公开(公告)号：US5889395A
公开(公告)日：1999-03-30
申请号：US49270
申请日：1998-03-27
申请人： Martin B. Lundberg
发明人： Martin B. Lundberg
IPC分类号： G05F3/24 , G05F3/26
CPC分类号： G05F3/247 , G05F3/262
摘要： An improved, high performance differential voltage regulator for high capacitance loads using a transistor-capacitor that will, while operating with voltages below 5 volts, have wide bandwidth, high current, and loop stability over a to a wide range of output capacitive loads.The regulator achieves this through first and second control loops coupled to a first one of a pair of differential transistors 2. The first of said control loops sends the output of the regulator to the gate of the first one of the differential transistors while the second of said control loops comprises a control transistor coupled to a transistor-capacitor and to a current mirror transistor controlled by the second differential transistor such that the output voltage may be compared to a reference voltage driving the first differential transistor to generate a differential current and provide differential voltage drives , via a current mirror, to the gate of the output transistor to provide an output capable of driving the gate of the output transistor from ground to voltage thereby providing wide bandwidth, high current, and loop stability to the circuit.
摘要翻译：一种改进的高性能差分电压调节器，用于使用晶体管电容器的高电容负载，该晶体管电容器将在低于5伏特的电压下工作，在宽范围的输出电容性负载下具有宽带宽，高电流和环路稳定性。调节器通过耦合到一对差分晶体管2中的第一个的第一和第二控制回路实现这一点。第一个控制回路将调节器的输出发送到第一个差分晶体管的栅极，而第二个所述控制回路包括耦合到晶体管电容器的控制晶体管和由第二差分晶体管控制的电流镜晶体管，使得可以将输出电压与驱动第一差分晶体管的参考电压进行比较以产生差分电流并提供差分电压驱动器通过电流镜向输出晶体管的栅极提供能够将输出晶体管的栅极从地电压驱动到电压的输出，从而为电路提供宽带宽，高电流和环路稳定性。

2. 发明授权

US5532970A No latency pipeline 失效
标题翻译：没有延迟管道
公开(公告)号：US5532970A
公开(公告)日：1996-07-02
申请号：US398334
申请日：1995-03-03
申请人： Edward Butler , Martin B. Lundberg , Pushkar U. Mokashi , Alfred L. Sartwell , Hemen R. Shah , Robert Tamlyn
发明人： Edward Butler , Martin B. Lundberg , Pushkar U. Mokashi , Alfred L. Sartwell , Hemen R. Shah , Robert Tamlyn
IPC分类号： G11C11/401 , G06T1/60 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1075 , G11C7/1039 , G11C7/1072
摘要： An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.
摘要翻译：一种用于增强串行存取存储器（SAM）性能的装置和方法，其包括消除第一位时钟周期等待时间的流水线技术。在视频DRAM（VDRAM）读取操作中，访问的VDRAM数据同时提供给SAM和主锁存器。在SAM数据的第二到第n位之前，VDRAM数据的第一位从主锁存器移动到存储器装置的辅助输出端口。

3. 发明授权

US06930506B2 Terminating resistor driver for high speed data communication 有权
标题翻译：终端电阻驱动器用于高速数据通信
公开(公告)号：US06930506B2
公开(公告)日：2005-08-16
申请号：US10065475
申请日：2002-10-22
申请人： Hayden C. Cranford, Jr. , Martin B. Lundberg
发明人： Hayden C. Cranford, Jr. , Martin B. Lundberg
IPC分类号： H03K19/00 , H04L25/02 , H03K17/16 , H03K19/0175
CPC分类号： H04L25/0278 , H03K19/0005 , H04L25/028 , H04L25/0282 , H04L25/0292
摘要： A method and structure for a driver circuit having a plurality of parallel resistors, where a total impedance of all the resistors equals an impedance of an associated transmission line and a switch adapted to combine the resistors to control an output level of the driver. The driver circuit's switch selectively connects the resistors to either a voltage high signal or a voltage low signal. The first set of the switches connect a voltage high signal to a first resistor of the resistors and a second set of switches connect a voltage low signal to a second resistor of the resistors. The switch has a matched pair of opposite type transistors. The driver circuit has balancing resistors connected to the switch, the balancing resistors are sized to balance the resistance within the driver circuit. The resistors are the balancing resistors and the drivers are connected to the switches.
摘要翻译：一种用于具有多个并联电阻器的驱动器电路的方法和结构，其中所有电阻器的总阻抗等于相关传输线路的阻抗，以及适于组合电阻器以控制驱动器的输出电平的开关。驱动器电路的开关选择性地将电阻器连接到电压高电平信号或电压低电平信号。第一组开关将电压高信号连接到电阻器的第一电阻器，第二组开关将电压低信号连接到电阻器的第二电阻器。开关具有一对相对的晶体管。驱动器电路具有连接到开关的平衡电阻器，平衡电阻器的尺寸用于平衡驱动器电路内的电阻。电阻是平衡电阻，驱动器连接到开关。

4. 发明授权

US5177374A Current mode gate drive for power MOS transistors 失效
标题翻译：功率MOS晶体管的电流模式门驱动
公开(公告)号：US5177374A
公开(公告)日：1993-01-05
申请号：US592148
申请日：1990-10-03
申请人： Gary D. Carpenter , Martin B. Lundberg
发明人： Gary D. Carpenter , Martin B. Lundberg
IPC分类号： H03F3/30 , H03F3/345 , H03F3/50
CPC分类号： H03F3/505 , H03F3/3455
摘要： A power amplifier having a power MOS transistor output device. The gate drive for the power device is a bidirectional current source. In one form of the gate driver circuit, the bidirectional current source includes the capability of controlling the liimts of the gate current, which in turn controls the slew rate of the power amplifier.

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