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    • 3. 发明授权
    • System for reducing power consumption and increasing speed of content-addressable memory
    • 用于降低功耗并提高内容可寻址存储器速度的系统
    • US08451640B2
    • 2013-05-28
    • US12930581
    • 2011-01-10
    • Christopher GronlundMark Winter
    • Christopher GronlundMark Winter
    • G11C15/00
    • G11C15/04G11C5/025G11C15/00G11C15/043
    • A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
    • 配置用于降低功耗和增加速度的内容可寻址存储器(CAM)系统包括实现堆叠架构的多个位单元。 每个位单元包括第一列中的一对堆叠存储元件和耦合到一对堆叠存储元件的对比电路和位于第二列中的CAM系统的匹配线。 堆叠架构导致匹配线长度缩短,从而降低CAM系统功耗并提高CAM系统速度。 在另一实施例中,被配置为降低功耗和增加速度的内容可寻址存储器(CAM)系统包括将编码数据存储在一对堆叠存储元件中。
    • 4. 发明申请
    • System for reducing power consumption and increasing speed of content-addressable memory
    • 用于降低功耗并提高内容可寻址存储器速度的系统
    • US20120147643A1
    • 2012-06-14
    • US12930581
    • 2011-01-10
    • Christopher GronlundMark Winter
    • Christopher GronlundMark Winter
    • G11C15/04G11C5/14
    • G11C15/04G11C5/025G11C15/00G11C15/043
    • According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
    • 根据一个公开的实施例,配置用于降低功耗和增加速度的内容可寻址存储器(CAM)系统包括实现堆叠架构的多个位单元。 每个位单元包括第一列中的一对堆叠存储元件和耦合到一对堆叠存储元件的对比电路和位于第二列中的CAM系统的匹配线。 堆叠架构导致匹配线长度缩短,从而降低CAM系统功耗并提高CAM系统速度。 在另一实施例中,被配置为降低功耗和增加速度的内容可寻址存储器(CAM)系统包括将编码数据存储在一对堆叠存储元件中。
    • 6. 发明授权
    • Performance monitor with memory ring oscillator
    • 具有内存环形振荡器的性能监视器
    • US09159378B2
    • 2015-10-13
    • US12930470
    • 2011-01-06
    • Mark WinterEric Hall
    • Mark WinterEric Hall
    • G01R31/3187G11C5/14G11C29/02G11C29/06G01R31/28
    • G11C5/147G01R31/2884G11C29/021G11C29/06
    • Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.
    • 公开了一种监视系统,其包括集成到半导体管芯中的至少一个性能监视器。 性能监视器包括至少一个包括多个级的环形振荡器。 每个级包括至少一个存储器件。 在一个实施例中,性能监视器还可以包括具有老化输入和使能输入的设置电路。 该设置电路能够将至少一个环形振荡器的输入信号设置为参考电压电平。 性能监视器被配置为产生以至少一个存储器件的性能为特征的环形延迟。 可以利用环延迟来缩放半导体管芯上的至少一个存储器件的工作电压。
    • 7. 发明申请
    • Performance monitor with memory ring oscillator
    • 具有内存环形振荡器的性能监视器
    • US20120146672A1
    • 2012-06-14
    • US12930470
    • 2011-01-06
    • Mark WinterEric Hall
    • Mark WinterEric Hall
    • G01R31/26G01R31/3187
    • G11C5/147G01R31/2884G11C29/021G11C29/06
    • Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.
    • 公开了一种监视系统,其包括集成到半导体管芯中的至少一个性能监视器。 性能监视器包括至少一个包括多个级的环形振荡器。 每个级包括至少一个存储器件。 在一个实施例中,性能监视器还可以包括具有老化输入和使能输入的设置电路。 该设置电路能够将至少一个环形振荡器的输入信号设置为参考电压电平。 性能监视器被配置为产生以至少一个存储器件的性能为特征的环形延迟。 可以利用环延迟来缩放半导体管芯上的至少一个存储器件的工作电压。
    • 8. 发明授权
    • Subscriber management system for a communication network
    • 用于通信网络的用户管理系统
    • US08126428B2
    • 2012-02-28
    • US12186451
    • 2008-08-05
    • Peter GelbmanJeffrey SewellMark Winter
    • Peter GelbmanJeffrey SewellMark Winter
    • H04M11/00H04M3/42
    • H04L12/14H04L12/1403H04L12/1425H04L12/1428H04L41/5003H04L47/2491
    • A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager 40, and an Application Manager 28, into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client 34, a Hotlining function 36, and a QoS SFA function 44 are located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.
    • 一种用于具有由网关节点耦合到分组交换网络的无线电接入网络的通信系统的订户管理系统。 该系统将三个现有技术的用户管理系统组件,DPI设备,QoS策略管理器40和应用管理器28整合到DPI平台中。 该系统还将功能重新定位到先前由现有技术网络中的网关节点提供的DPI平台。 具体来说,会计客户端34,热线功能36和QoS SFA功能44位于DPI平台。 通过将网络组件和重定位功能整合到DPI平台,可以减少网络中的控制接口数量。 此外,不同供应商生产的网络组件可以更容易地集成。 还提供了一种在系统中实现热线的方法。
    • 9. 发明申请
    • SUBSCRIBER MANAGEMENT SYSTEM FOR A COMMUNICATION NETWORK
    • 用于通信网络的订户管理系统
    • US20090042537A1
    • 2009-02-12
    • US12186451
    • 2008-08-05
    • Peter GelbmanJeffrey SewellMark Winter
    • Peter GelbmanJeffrey SewellMark Winter
    • H04M15/00H04M3/42
    • H04L12/14H04L12/1403H04L12/1425H04L12/1428H04L41/5003H04L47/2491
    • A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager 40, and an Application Manager 28, into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client 34, a Hotlining function 36, and a QoS SFA function 44 are located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.
    • 一种用于具有由网关节点耦合到分组交换网络的无线接入网络的通信系统的用户管理系统。 该系统将三个现有技术的用户管理系统组件,DPI设备,QoS策略管理器40和应用管理器28整合到DPI平台中。 该系统还将功能重新定位到先前由现有技术网络中的网关节点提供的DPI平台。 具体来说,会计客户端34,热线功能36和QoS SFA功能44位于DPI平台。 通过将网络组件和重定位功能整合到DPI平台,可以减少网络中的控制接口数量。 此外,不同供应商生产的网络组件可以更容易地集成。 还提供了一种在系统中实现热线的方法。