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1. 发明申请

US20050289413A1 Integrated semiconductor memory 有权
标题翻译：集成半导体存储器
公开(公告)号：US20050289413A1
公开(公告)日：2005-12-29
申请号：US11145192
申请日：2005-06-06
申请人： Joerg Vollrath , Marcin Gnat , Aurel Campenhausen , Frank Schroeppel
发明人： Joerg Vollrath , Marcin Gnat , Aurel Campenhausen , Frank Schroeppel
IPC分类号： G11B20/00 , G11B20/18 , G11B27/36 , G11C29/00 , G11C29/14 , G11C29/38
CPC分类号： G11C29/1201 , G11C29/14 , G11C29/38
摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.
摘要翻译：集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到输入侧的组合电路。如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。

2. 发明申请

US20050249002A1 Integrated semiconductor memory 有权
标题翻译：集成半导体存储器
公开(公告)号：US20050249002A1
公开(公告)日：2005-11-10
申请号：US11123221
申请日：2005-05-06
申请人： Jurgen Auge , Manfred Proll , Jorg Kliewer , Frank Schroeppel
发明人： Jurgen Auge , Manfred Proll , Jorg Kliewer , Frank Schroeppel
IPC分类号： G11C7/00 , G11C29/00 , G11C29/48
CPC分类号： G11C29/48
摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.
摘要翻译：集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。阈值由控制电路预先定义。编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。在测试结束之后，通过输出端读出编程元件的状态。该方案可以推断集成半导体存储器的可能的故障原因。

3. 发明授权

US07313741B2 Integrated semiconductor memory 有权
标题翻译：集成半导体存储器
公开(公告)号：US07313741B2
公开(公告)日：2007-12-25
申请号：US11145192
申请日：2005-06-06
申请人： Joerg Vollrath , Marcin Gnat , Aurel von Campenhausen , Frank Schroeppel
发明人： Joerg Vollrath , Marcin Gnat , Aurel von Campenhausen , Frank Schroeppel
IPC分类号： G01R31/28
CPC分类号： G11C29/1201 , G11C29/14 , G11C29/38
摘要： An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.
摘要翻译：集成半导体存储器包括存储第一数据记录的存储器单元具有至少一个具有第一或第二数据值的数据，而第二数据记录具有至少一个具有第一或第二数据值的数据。集成半导体存储器具有组合电路，其从在输入侧馈送到组合电路的数据记录在输出侧产生第三数据记录，以基于第三数据记录来确定第一和第二数据记录是否被馈送到输入侧的组合电路。如果第一和第二数据记录被馈送到输入侧的组合电路，则组合电路产生具有第一数据值的第三数据记录的数据。

4. 发明授权

US07206980B2 Integrated semiconductor memory 有权
标题翻译：集成半导体存储器
公开(公告)号：US07206980B2
公开(公告)日：2007-04-17
申请号：US11123221
申请日：2005-05-06
申请人： Jürgen Auge , Manfred Pröll , Jörg Kliewer , Frank Schroeppel
发明人： Jürgen Auge , Manfred Pröll , Jörg Kliewer , Frank Schroeppel
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/48
摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.
摘要翻译：集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。阈值由控制电路预先定义。编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。在测试结束之后，通过输出端读出编程元件的状态。该方案可以推断集成半导体存储器的可能的故障原因。

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