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1. 发明申请

US20090198973A1 PROCESSING CIRCUIT 审中-公开
标题翻译：加工电路
公开(公告)号：US20090198973A1
公开(公告)日：2009-08-06
申请号：US12360878
申请日：2009-01-28
申请人： Kazuhisa IIZUKA , Makoto OZONE
发明人： Kazuhisa IIZUKA , Makoto OZONE
IPC分类号： G06F9/44
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17728
摘要： A processing circuit according to the present invention includes a plurality of logic circuits (designated as L11, . . . , and L44) formed by arranging in arrays and is configured to input an output from a logic circuit to the logic circuit located on the following row. Each of the plurality of logic circuits includes an operation circuit (ALU) configured to perform an operation on inputted data; and a selecting unit (MUX) configured to select and output any one of an operation output from the operation circuit or an operation output from the logic circuit located on the preceding row.
摘要翻译：根据本发明的处理电路包括通过排列成阵列形成的多个逻辑电路（指定为L11，...和L44），并被配置为将来自逻辑电路的输出输入到位于以下的逻辑电路行。多个逻辑电路中的每一个包括被配置为对输入的数据执行操作的操作电路（ALU）以及选择单元（MUX），被配置为选择和输出从所述运算电路输出的运算或从位于前一行的逻辑电路输出的运算中的任何一个。

2. 发明申请

US20060048113A1 Data flow graph processing method and processing apparatus provided with reconfigurable circuit 有权
标题翻译：数据流图处理方法和处理装置配有可重构电路
公开(公告)号：US20060048113A1
公开(公告)日：2006-03-02
申请号：US11212598
申请日：2005-08-29
申请人： Makoto Ozone , Hiroshi Nakajima , Tatsuo Hiramatsu , Katsunori Hirase , Makoto Okada
发明人： Makoto Ozone , Hiroshi Nakajima , Tatsuo Hiramatsu , Katsunori Hirase , Makoto Okada
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.
摘要翻译：数据流图处理方法将描述目标操作的程序划分为两个或更多个子程序，并将两个或多个子程序中的每一个子程序转换为表示在顺序执行的操作之间的执行中依赖性的数据流图（DFG）。还产生指示对应于各个子程序的DFG的执行顺序的流量数据。 DFG被转换成配置数据，流数据被转换成控制数据。

3. 发明授权

US07941794B2 Data flow graph processing method and processing apparatus provided with reconfigurable circuit 有权
标题翻译：数据流图处理方法和处理装置配有可重构电路
公开(公告)号：US07941794B2
公开(公告)日：2011-05-10
申请号：US11212598
申请日：2005-08-29
申请人： Makoto Ozone , Hiroshi Nakajima , Tatsuo Hiramatsu , Katsunori Hirase , Makoto Okada
发明人： Makoto Ozone , Hiroshi Nakajima , Tatsuo Hiramatsu , Katsunori Hirase , Makoto Okada
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F8/433
摘要： A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.
摘要翻译：数据流图处理方法将描述目标操作的程序划分为两个或更多个子程序，并将两个或多个子程序中的每一个子程序转换为表示在顺序执行的操作之间的执行中依赖性的数据流图（DFG）。还产生指示对应于各个子程序的DFG的执行顺序的流量数据。 DFG被转换成配置数据，流数据被转换成控制数据。

4. 发明授权

US07895586B2 Data flow graph processing method, reconfigurable circuit and processing apparatus 有权
标题翻译：数据流图处理方法，可重构电路及处理装置
公开(公告)号：US07895586B2
公开(公告)日：2011-02-22
申请号：US11155667
申请日：2005-06-20
申请人： Makoto Ozone
发明人： Makoto Ozone
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F15/7867 , G06F17/5045
摘要： A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in the sub-DFG is configured to be equal to or fewer than the number of logic circuits per row in the reconfigurable circuit. Subsequently, the sub-DFGs are joined so as to generate a joined DFG. The number of columns in the joined DFG is also configured to be equal to or fewer than the number of columns per row in the reconfigurable circuit. The joined DFG is redivided to sizes with number of rows equal to or fewer than the number of rows in the reconfigurable circuit, so as to generate subjoined DFGs mappable into the reconfigurable circuit.
摘要翻译：数据流图处理方法根据可重构电路中设置的电路中的逻辑电路的数量，将生成的至少一个DFG分割为多个子DFG。当可重构电路具有包括多行连接的结构时，子DFG中的列数被配置为等于或小于可重新配置电路中每行逻辑电路的数量。随后，子DFG被连接以产生连接的DFG。连接的DFG中的列数也被配置为等于或小于可重构电路中每行的列数。连接的DFG被重新划分为等于或少于可重构电路中的行数的行数，以便生成可映射到可重新配置电路中的子联DFG。

5. 发明申请

US20070038971A1 Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices 审中-公开
标题翻译：具有可重构电路的处理器件，集成电路器件和使用这些器件的处理方法
公开(公告)号：US20070038971A1
公开(公告)日：2007-02-15
申请号：US10573970
申请日：2004-07-09
申请人： Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Okada , Makoto Ozone
发明人： Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Okada , Makoto Ozone
IPC分类号： G06F17/50
CPC分类号： G06F15/7867
摘要： In the processing device in accordance with the present invention, a plurality of divided circuits obtained by dividing one circuit are successively configured on a reconfigurable circuit, an operation is executed by the divided circuits by feeding back an output of one divided circuit to a next divided circuit, and an output is taken out from the last configured divided circuit. As a feedback path, a path portion is formed, which connects the output of the reconfigurable circuit to its input. By successively configuring the divided circuits, one circuit as a whole can be implemented.
摘要翻译：在根据本发明的处理装置中，通过划分一个电路获得的多个分割电路被连续地配置在可重新配置电路上，通过将一个划分电路的输出反馈到下一个被划分的电路电路，并从最后配置的分频电路中取出输出。作为反馈路径，形成路径部分，其将可重构电路的输出连接到其输入。通过连续配置划分的电路，可以实现一个电路作为整体。

6. 发明授权

US07953956B2 Reconfigurable circuit with a limitation on connection and method of determining functions of logic circuits in the reconfigurable circuit 失效
标题翻译：具有限制连接的可重构电路和确定可重构电路中逻辑电路功能的方法
公开(公告)号：US07953956B2
公开(公告)日：2011-05-31
申请号：US11016904
申请日：2004-12-21
申请人： Makoto Okada , Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Ozone
发明人： Makoto Okada , Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Ozone
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/1778 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.
摘要翻译：降低电路规模的可重构电路。本发明的可重构电路包括能够改变功能的多个ALU。多个ALU被布置成矩阵。在ALU的各级之间提供能够选择性地建立ALU之间的连接的至少一个连接单元。该连接单元不旨在允许在相邻级中的所有逻辑电路之间的连接，而是被配置为使得逻辑电路可以仅与属于其它级的一些逻辑电路连接。连接限制允许减小电路规模。

7. 发明申请

US20050283768A1 Data flow graph processing method, reconfigurable circuit and processing apparatus 有权
标题翻译：数据流图处理方法，可重构电路及处理装置
公开(公告)号：US20050283768A1
公开(公告)日：2005-12-22
申请号：US11155667
申请日：2005-06-20
申请人： Makoto Ozone
发明人： Makoto Ozone
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F15/7867 , G06F17/5045
摘要： A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in the sub-DFG is configured to be equal to or fewer than the number of logic circuits per row in the reconfigurable circuit. Subsequently, the sub-DFGs are joined so as to generate a joined DFG. The number of columns in the joined DFG is also configured to be equal to or fewer than the number of columns per row in the reconfigurable circuit. The joined DFG is redivided to sizes with number of rows equal to or fewer than the number of rows in the reconfigurable circuit, so as to generate subjoined DFGs mappable into the reconfigurable circuit.
摘要翻译：数据流图处理方法根据可重构电路中设置的电路中的逻辑电路的数量，将生成的至少一个DFG分割为多个子DFG。当可重构电路具有包括多行连接的结构时，子DFG中的列数被配置为等于或小于可重新配置电路中每行逻辑电路的数量。随后，子DFG被连接以产生连接的DFG。连接的DFG中的列数也被配置为等于或小于可重构电路中每行的列数。连接的DFG被重新划分为等于或少于可重构电路中的行数的行数，以便生成可映射到可重新配置电路中的子联DFG。

8. 发明申请

US20050134308A1 Reconfigurable circuit, processor having reconfigurable circuit, method of determining functions of logic circuits in reconfigurable circuit, method of generating circuit, and circuit 失效
标题翻译：可重构电路，具有可重构电路的处理器，可重构电路中逻辑电路的功能确定方法，发电电路方法及电路
公开(公告)号：US20050134308A1
公开(公告)日：2005-06-23
申请号：US11016904
申请日：2004-12-21
申请人： Makoto Okada , Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Ozone
发明人： Makoto Okada , Tatsuo Hiramatsu , Hiroshi Nakajima , Makoto Ozone
IPC分类号： G06F7/00 , G06F15/78 , G06F17/50 , H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： G06F15/7867 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/1778 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.
摘要翻译：降低电路规模的可重构电路。本发明的可重构电路包括能够改变功能的多个ALU。多个ALU被布置成矩阵。在ALU的各级之间提供能够选择性地建立ALU之间的连接的至少一个连接单元。该连接单元不旨在允许在相邻级中的所有逻辑电路之间的连接，而是被配置为使得逻辑电路可以仅与属于其它级的一些逻辑电路连接。连接限制允许减小电路规模。

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