专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06633542B1 Method of establishing a flow in an ATM based MPOA network 失效
标题翻译：在基于ATM的MPOA网络中建立流的方法
公开(公告)号：US06633542B1
公开(公告)日：2003-10-14
申请号：US09474686
申请日：1999-12-29
申请人： Sarit Shani Natanson , Benny Gershon , Lior Katzri
发明人： Sarit Shani Natanson , Benny Gershon , Lior Katzri
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L45/22 , H04L45/38 , H04L2012/562 , H04L2012/5669
摘要： A method of controlling the route used for a flow in an environment comprising a default routing path and a shortcut path in an MPOA enabled ATM based network. A data field is added to the Ingress Cache table in the Ingress MPOA Client (I-MPC) to indicate whether the flow is to be routed through an MPOA shortcut towards the Egress MPOA Client (E-MPC) or is to be routed through the default path towards the Ingress MPOA Server (I-MPS). A first embodiment comprises a method of controlling the routing of a data flow from a source to a destination for security purposes. A second embodiment comprises a method of load sharing a plurality of data flows. A third embodiment comprises a method of learning about past MPOA resolution successes and failures and utilizing past establishment history to bypass the MPOA resolution process.
摘要翻译：一种用于在包括基于MPOA的ATM基网络中的默认路由路径和快捷路径的环境中用于流的路由的方法。数据字段被添加到Ingress MPOA客户端（I-MPC）中的入口缓存表中，以指示流是否通过MPOA快捷方式路由到出口MPOA客户端（E-MPC），或者通过入口MPOA服务器（I-MPS）的默认路径。为了安全起见，第一实施例包括控制数据流从源到目的地的路由的方法。第二实施例包括负载共享多个数据流的方法。第三个实施例包括一种学习过去MPOA分辨率成功和失败的方法，并利用过去的建立历史绕过MPOA解析过程。

2. 发明授权

US06563830B1 Multicast registration of all multicast flows in an asynchronous transfer mode based emulated LAN 失效
标题翻译：基于仿真LAN的异步传输模式中的所有组播流的组播注册
公开(公告)号：US06563830B1
公开(公告)日：2003-05-13
申请号：US09537038
申请日：2000-03-28
申请人： Benny Gershon , Lior Katzri , Yuri Shwartsburd
发明人： Benny Gershon , Lior Katzri , Yuri Shwartsburd
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L12/185 , H04L12/1886 , H04L12/2801 , H04L12/4608 , H04L2012/5621
摘要： An apparatus for and a method of implementing multicast registration in an ATM based ELAN. The present invention provides a mechanism for a LEC to register to receive all multicast group traffic flows without requiring the LEC to generate a separate request for each multicast MAC address. The mechanism of the present invention provides means for a LEC to register to receive all multicast flows by defining an ‘all_multicast’ TLV and including this TLV in the LE_REGISTER_REQUEST request message sent by the LEC. The LEC, LES and SMS are modified to perform the multicast registration/unregistration method of the present invention. The LEC generates the LE_REGISTER_REQUEST message and includes the all_multicast TLV indicating that the LEC desires to receive all multicast traffic flows in the ELAN. The LES, upon receipt of such an all_multicast TLV, adds the LEC to its list of LECs to receive all multicast traffic and communicates the related information to the SMS. The SMS is adapted to add the LEC to each of the multicast groups currently maintained by the SMS. A similar symmetric process occurs in the event a LEC wishes to stop receiving all multicast traffic.
摘要翻译：一种在基于ATM的ELAN中实现多播注册的装置和方法。本发明提供了一种用于LEC注册以接收所有多播组业务流的机制，而不需要LEC为每个组播MAC地址生成单独的请求。本发明的机制提供了用于通过在LEC发送的LE_REGISTER_REQUEST请求消息中定义“全组播”TLV并包括该TLV来注册以接收所有多播流的装置，LEC，LES和SMS被修改为执行本发明的组播注册/注册方法，LEC生成LE_REGISTER_REQUEST消息，并且包括指示LEC希望在ELAN中接收所有多播业务流的全部组播TLV，LES在接收到这样的全组播TLV时，将LEC 到其列出的LEC接收所有多播流量并将相关信息传送给SMS，SMS适于将LEC添加到由SMS维护的每个多播组中，类似的对称过程发生在LEC希望的情况下停止接收所有组播流量。

3. 发明授权

US06643289B1 Method of MPOA status change notification 失效
标题翻译： MPOA状态变更通知方法
公开(公告)号：US06643289B1
公开(公告)日：2003-11-04
申请号：US09474687
申请日：1999-12-29
申请人： Sarit Shani Natanson , Lior Katzri , Benny Gershon , Ronit Aizicovich
发明人： Sarit Shani Natanson , Lior Katzri , Benny Gershon , Ronit Aizicovich
IPC分类号： H04L1256
CPC分类号： H04L12/4608
摘要： A method of notification and handling of device status changes in MPOA enabled ATM based networks. In a first method notification of changes in device status configuration are provided by selectively releasing one or more Data Direct VCs that were previously established be LECs connecting MPOA Servers and MPOA Clients. An MPOA Server, upon detecting a change to its device configuration status, releases the Data Direct VCs connecting its associated LEC to known MPSs and MPCs that are neighbors to it. All MPOA devices for which a Data Direct VC was released delete all LE_ARP cache entries associated with the ATM destination of the released Data Direct VC. In a second method, each MPOA device periodically sends keep alive messages as targetless LE_ARP messages having a time to live TLV appended. An MPOA device receiving the keep alive message, refreshes (i.e., restarts) a validation timer for each association made by the corresponding MPOA identification TLV. If the validation timer expires before being refreshed, the MPOA device deletes all associations previously made by the corresponding MPOA identification TLV.
摘要翻译：一种在MPOA启用的ATM网络中通知和处理设备状态变化的方法。在第一种方法中，通过选择性地释放先前建立的一个或多个数据直接VC，连接MPOA服务器和MPOA客户端的LEC来提供设备状态配置变化的通知。 MPOA服务器在检测到其设备配置状态的变化后，将连接其相关联的LEC的Data Direct VC释放到与其相邻的已知MPS和MPC。发布Data Direct VC的所有MPOA设备都会删除与释放的Data Direct VC的ATM目的地相关联的所有LE_ARP缓存条目。在第二种方法中，每个MPOA设备周期性地发送保持活动消息作为具有附加时间的TLV的无目标LE_ARP消息。接收保持活动消息的MPOA设备，刷新（即，重新启动）由相应的MPOA标识TLV进行的每个关联的验证定时器。如果验证定时器在刷新之前到期，则MPOA设备将删除先前由相应MPOA标识TLV进行的所有关联。

4. 发明授权

US06639901B1 Apparatus for and method for supporting 802.1Q VLAN tagging with independent VLAN learning in LAN emulation networks 有权
标题翻译：用于在LAN仿真网络中支持具有独立VLAN学习的802.1Q VLAN标记的设备和方法
公开(公告)号：US06639901B1
公开(公告)日：2003-10-28
申请号：US09490750
申请日：2000-01-24
申请人： Lior Katzri , Opher Yaron
发明人： Lior Katzri , Opher Yaron
IPC分类号： H04L1228
CPC分类号： H04L45/00 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/5601 , H04L45/505 , H04L2012/5621
摘要： An apparatus for and a method of extending the ATM Forum LAN Emulation standard to support 802.1Q VLAN tagging with Independent VLAN Learning. A standard LEC entity is modified to perform the VLAN tagging method that supports Independent VLAN Learning. Since the LES may also respond to LE_ARP messages, it is optionally modified to perform the VLAN tagging method of the invention so as to provide support for 802.1Q Independent VLAN Learning. Support for 802.1Q Independent VLAN Learning is provided by adding a VLAN-ID TLV to LAN Emulation control messages such as LE_ARP and LE_REGISTER messages. The TLV added comprises the VLAN Tag Header information that is normally carried by the Ethernet frame in 802.1Q networks.
摘要翻译：一种用于扩展ATM论坛LAN仿真标准以支持具有独立VLAN学习的802.1Q VLAN标记的装置和方法。修改标准的LEC实体来执行支持独立VLAN学习的VLAN标记方法。由于LES还可以响应LE_ARP消息，所以可选地修改以执行本发明的VLAN标签方法，以便为802.1Q独立VLAN学习提供支持。通过向LAN仿真控制消息（如LE_ARP和LE_REGISTER消息）添加VLAN-ID TLV来提供对802.1Q独立VLAN学习的支持。添加的TLV包括通常由802.1Q网络中的以太网帧携带的VLAN Tag头信息。

5. 发明授权

US06606321B1 Method of establishing MPOA shortcut virtual channel connections 失效
标题翻译：建立MPOA快捷虚拟通道连接的方法
公开(公告)号：US06606321B1
公开(公告)日：2003-08-12
申请号：US09474675
申请日：1999-12-29
申请人： Sarit Shani Natanson , Lior Katzri , Benny Gershon , Dror Goldstein
发明人： Sarit Shani Natanson , Lior Katzri , Benny Gershon , Dror Goldstein
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L2012/563 , H04L2012/5669
摘要： A method of establishing calls between an ingress MPC (the calling party) and an egress MPC (the called party) in MPOA enabled ATM based networks. The call establishment method utilizes the call request SETUP, CONNECT and CONNECT_ACK messages in creating the shortcut VCC between ingress and egress MPCs. The calling party is adapted to send a READY_IND message in a reliable manner to the called party indicating that it is ready to receive frames over the shortcut VCC. The called party starts sending data over the shortcut VCC only when it knows that the calling party is ready. The called party knows the calling party is ready upon receipt of a READY_IND message or at least one data frame on the shortcut VCC. The calling party knows that the called party is ready to receive frames when it receives the CONNECT message. Since the READY_IND message sent by the calling party may get lost, the calling party is adapted to re-send the READY_IND message repeatedly until it is certain the called party has received it. The calling party utilizes a timer whereupon expiration, the READY_IND message is re-sent to the called party and the timer is restarted.
摘要翻译：在MPOA启用的基于ATM的网络中，在入口MPC（主叫方）和出口MPC（被叫方）之间建立呼叫的方法。呼叫建立方法利用呼叫请求SETUP，CONNECT和CONNECT_ACK消息在入口和出口MPC之间创建快捷方式VCC。呼叫方适于以可靠的方式向被叫方发送READY_IND消息，指示其准备好通过快捷方式VCC接收帧。被叫方开始通过快捷方式VCC发送数据，只有当主叫方已经准备好了。被叫方知道呼叫方在接收到READY_IND消息或快捷方式VCC上的至少一个数据帧时准备就绪。主叫方知道被叫方在接收到CONNECT消息时准备好接收帧。由于主叫方发送的READY_IND消息可能会丢失，所以主叫方重复发送READY_IND消息，直到确定被叫方已经收到它为止。主叫方利用一个定时器到期，READY_IND消息被重新发送到被叫方，重启定时器。

6. 发明授权

US5596764A Debug mechanism for parallel-operating DSP module and CPU core 失效
标题翻译：并行操作DSP模块和CPU内核的调试机制
公开(公告)号：US5596764A
公开(公告)日：1997-01-21
申请号：US307385
申请日：1994-09-14
申请人： Gideon Intrater , Lior Katzri , Omri Viner , Raya Levitan , Yehezkel Tzadik
发明人： Gideon Intrater , Lior Katzri , Omri Viner , Raya Levitan , Yehezkel Tzadik
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F9/22 , G06F9/30
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

7. 发明授权

US5592677A Integrated data processing system including CPU core and parallel, independently operating DSP module 失效
标题翻译：集成数据处理系统包括CPU内核和并行，独立运行DSP模块
公开(公告)号：US5592677A
公开(公告)日：1997-01-07
申请号：US246554
申请日：1994-05-19
申请人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
发明人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/00
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.
摘要翻译：集成的数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

8. 发明授权

US5590357A Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme 失效
标题翻译：集成CPU内核和并行，独立运行DSP模块和时间关键的核心优先级方案
公开(公告)号：US5590357A
公开(公告)日：1996-12-31
申请号：US301739
申请日：1994-09-06
申请人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
发明人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/12
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 OP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式