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1. 发明授权

US5519879A Integrated circuit having CPU and DSP for executing vector lattice propagation instruction and updating values of vector Z in a single instruction cycle 失效
标题翻译：具有用于执行向量网格传播指令的CPU和DSP的集成电路，并且在单个指令周期中更新向量Z的值
公开(公告)号：US5519879A
公开(公告)日：1996-05-21
申请号：US296642
申请日：1994-08-26
申请人： Iddo Carmon
发明人： Iddo Carmon
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/00
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data. The DSP module includes a lattice filter mechanism for executing a single instruction to update propagating values of a vector responsive to the externally provided signal.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。 DSP模块包括一个晶格滤波器机构，用于响应于外部提供的信号执行单个指令来更新向量的传播值。

2. 发明授权

US5625828A Parallel operating CPU core and DSP module for executing sequence of vector DSP code instructions to generate decoded constellation points in QAM/TCM modem application 失效
标题翻译：并行运行CPU内核和DSP模块，用于执行矢量DSP代码指令序列，以在QAM / TCM调制解调器应用中生成解码的星座点
公开(公告)号：US5625828A
公开(公告)日：1997-04-29
申请号：US271204
申请日：1994-07-01
申请人： Iddo Carmon , Itael Fraenkel , Omri Viner , Ronny Cohen
发明人： Iddo Carmon , Itael Fraenkel , Omri Viner , Ronny Cohen
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/00 , G06F15/16
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. The system executes a novel QAM.backslash.TCM modem algorithm.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。系统执行新颖的QAM + 544 TCM调制解调器算法。

3. 发明授权

US5592677A Integrated data processing system including CPU core and parallel, independently operating DSP module 失效
标题翻译：集成数据处理系统包括CPU内核和并行，独立运行DSP模块
公开(公告)号：US5592677A
公开(公告)日：1997-01-07
申请号：US246554
申请日：1994-05-19
申请人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
发明人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/00
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.
摘要翻译：集成的数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

4. 发明授权

US5590357A Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme 失效
标题翻译：集成CPU内核和并行，独立运行DSP模块和时间关键的核心优先级方案
公开(公告)号：US5590357A
公开(公告)日：1996-12-31
申请号：US301739
申请日：1994-09-06
申请人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
发明人： Amos Intrater , Andy Birenbaum , Gideon Intrater , Iddo Carmon , Ilan Shimony , Itael Fraenkel , Lev Epstein , Lior Katzri , Omri Viner , Raya Levitan , Ronny Cohen , Sidi Yomtov , Yehezkel Tzadik , Zvi Greenfeld , Israel Greiss , Oved Oz , Yachin Afek , Meir Tsadik , Moshe Doron , Alberto Sandbank
IPC分类号： G06F9/32 , G06F9/38 , G06F11/36 , G06F13/24 , G06F15/78 , H04L27/38 , G06F13/12
CPC分类号： G06F11/3648 , G06F11/3656 , G06F11/3664 , G06F13/24 , G06F15/7842 , G06F9/30167 , G06F9/32 , G06F9/3879 , H04L27/38
摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.
摘要翻译：集成数据处理系统包括用于传送指令和数据的共享内部总线。共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线。通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 OP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

5. 发明授权

US5200981A Fine timing recovery for QAM modem receiver 失效
标题翻译： QAM调制解调器接收机的精确定时恢复
公开(公告)号：US5200981A
公开(公告)日：1993-04-06
申请号：US902511
申请日：1992-06-22
申请人： Iddo Carmon
发明人： Iddo Carmon
IPC分类号： H04L7/033
CPC分类号： H04L7/0334
摘要： A QAM modem receiver performs fine-timing on a baseband signal sampled at two complex points per symbol. Based on this information, the algebraic signs of the second derivative of the baseband signal are estimated. These signs, computed separately for the real and imaginary axes, are used to a make local decision regarding convexity/concavity of the baseband signal. By accumulating these local decisions over an appropriate time interval, a global decision is reached regarding the sampling point position relative to the baseband signal maxima/minima. Based on this global decision, a correction command is issued to the modem's analog front end to either advance or delay the timing.
摘要翻译： QAM调制解调器接收机对每个符号两个复杂点采样的基带信号执行精确定时。基于该信息，估计基带信号的二阶导数的代数符号。对于实心轴和虚轴分别计算的这些符号用于对基带信号的凸/凹度进行局部判定。通过在适当的时间间隔内累积这些局部决策，就相对于基带信号最大值/最小值的采样点位置达成全局判定。基于这个全局决定，向调制解调器的模拟前端发出校正命令，以提前或延迟时序。

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