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1. 发明授权

US07401126B2 Transaction switch and network interface adapter incorporating same 有权
标题翻译：交易开关和网络接口适配器结合相同
公开(公告)号：US07401126B2
公开(公告)日：2008-07-15
申请号：US09817008
申请日：2001-03-23
申请人： Richard E. Pekkala , Christopher J. Pettey , Lawrence H. Rubin , Shaun V. Wandler
发明人： Richard E. Pekkala , Christopher J. Pettey , Lawrence H. Rubin , Shaun V. Wandler
IPC分类号： G06F15/16
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027
摘要： A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely packetized interfaces like InfiniBand and addressed data interfaces like PCI. The transaction switch also switches transactions commanding data transfers between the disparate protocol data interfaces and between those of the data interfaces having like protocols. For example, the transaction switch enables a hybrid InfiniBand channel adapter/switch to perform both InfiniBand packet to local bus protocol data transfers through the shared memory as well as InfiniBand packet switching between the multiple InfiniBand interfaces. The transactions are tailored for each interface type to include information needed by the particular interface type to perform a data transfer. The shared buffer memory, dynamically allocated by the transaction switch on a first-come-first serve basis, results in more efficient use of precious buffering resources than in a statically allocated scheme.
摘要翻译：一种交易开关和集成电路，其包括用于在支持不同数据协议的多个数据接口之间的共享存储器切换数据，即诸如InfiniBand的分组接口和诸如PCI的寻址数据接口。事务处理交换机还切换命令在不同的协议数据接口之间以及具有类似协议的数据接口之间的数据传输的事务。例如，事务交换机使混合InfiniBand通道适配器/交换机能够通过共享内存来执行InfiniBand数据包到本地总线协议数据传输以及多个InfiniBand接口之间的InfiniBand数据包交换。交易针对每个接口类型量身定制，以包括特定接口类型所需的信息来执行数据传输。以先到先得的方式动态分配的共享缓冲存储器比静态分配方案更有效地利用了宝贵的缓冲资源。

2. 发明授权

US06594712B1 Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link 有权
标题翻译： Infiniband通道适配器，用于在PCI总线和infiniband链路之间执行直接DMA
公开(公告)号：US06594712B1
公开(公告)日：2003-07-15
申请号：US09693405
申请日：2000-10-20
申请人： Christopher Pettey , Lawrence H. Rubin
发明人： Christopher Pettey , Lawrence H. Rubin
IPC分类号： G06F1328
CPC分类号： G06F13/404 , G06F13/28 , G06F13/385
摘要： An Infiniband channel adapter for performing direct data transfers between a PCI bus and an Infiniband link without double-buffering the data in system memory. A local processor programs the channel adapter to decode addresses in a range of the PCI bus address space dedicated to direct transfers. When an I/O controller attached to the PCI bus transfers data from an I/O device to an address in the dedicated range, the channel adapter receives the data into an internal buffer and creates an Infiniband RDMA Write packet for transmission to virtual address within a remote Infiniband node. When the channel adapter receives an Infiniband RDMA Read Response packet, the channel adapter provides the packet payload data to the I/O controller at a PCI address in the dedicated range. A plurality of programmable address range registers facilitates multiple of the direct transfers concurrently by dividing the dedicated address range into multiple sub-ranges. The address range registers enable random mapping between the address sub-ranges and multiple internal buffers for receiving and transmitting Infiniband RDMA packets.
摘要翻译：一个Infiniband通道适配器，用于在PCI总线和Infiniband链路之间执行直接数据传输，无需双重缓冲系统内存中的数据。本地处理器对通道适配器进行编程，以对专用于直接传输的PCI总线地址空间范围内的地址进行解码。当连接到PCI总线的I / O控制器将数据从I / O设备传送到专用范围中的地址时，通道适配器将数据接收到内部缓冲区，并创建一个Infiniband RDMA写入数据包，以传输到虚拟地址远程Infiniband节点。当通道适配器接收到Infiniband RDMA读取响应数据包时，通道适配器将数据包有效负载数据提供给专用范围内的PCI地址的I / O控制器。多个可编程地址范围寄存器通过将专用地址范围分成多个子范围来同时促进多个直接传输。地址范围寄存器允许地址子范围和多个内部缓冲区之间的随机映射，用于接收和发送Infiniband RDMA数据包。

3. 发明授权

US5778432A Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register 失效
标题翻译：用于响应于高速缓存刷新控制位寄存器而执行用于刷新和非刷新操作的不同高速缓存替换算法的方法和装置
公开(公告)号：US5778432A
公开(公告)日：1998-07-07
申请号：US674050
申请日：1996-07-01
申请人： Lawrence H. Rubin , Paul A. Reed
发明人： Lawrence H. Rubin , Paul A. Reed
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/127
摘要： A method and apparatus for efficiently performing a cache operation in a processor (70) for both flushing and non-flushing. One embodiment uses a cache flush control bit (100) in a data cache (90) to determine whether or not to ignore valid bits (130) during a pseudo least recently used (LRU) replacement algorithm. When the replacement algorithm is being used for flushing the data cache (90), the valid bits (130) are not used in order to make the algorithm more efficient. If the valid bits (130) are ignored, then the least recently used bits (120) are used to select the cache line that will be replaced. However, when the replacement algorithm is being used for a non-flushing replacement purpose, the valid bits (130) are used first, followed by the plurality of least recently used bits (120), to select the cache line that will be replaced.
摘要翻译：一种用于在处理器（70）中有效执行高速缓存操作以用于冲洗和非冲洗的方法和装置。一个实施例在数据高速缓存（90）中使用高速缓存刷新控制位（100）来确定是否在伪最近最少使用（LRU）替换算法期间忽略有效位（130）。当替换算法用于刷新数据高速缓存（90）时，不使用有效位（130），以使算法更有效。如果忽略有效位（130），则使用最近最少使用的比特（120）来选择将被替换的高速缓存行。然而，当替换算法被用于非刷新替换目的时，首先使用有效比特（130），随后使用多个最近最少使用的比特（120）来选择将被替换的高速缓存线。

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