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1. 发明授权

US09916449B2 Identification of backdoors and backdoor triggers 有权
公开(公告)号：US09916449B2
公开(公告)日：2018-03-13
申请号：US14773104
申请日：2013-11-12
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , Lakshminarasimhan Sethumadhavan , Adam Waksman , Matthew Suozzo
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman , Matthew Suozzo
IPC分类号： G06F21/56 , G06F21/71 , H04L29/06 , G06F11/263
CPC分类号： G06F21/566 , G06F11/263 , G06F21/56 , G06F21/71 , H04L63/1466
摘要： Disclosed are devices, systems, apparatus, methods, products, media, and other implementations, including a method that includes computing for one or more inputs of a circuit associated metrics representative of degree of influence that values of each of the one or more inputs have on at least one output dependent on the one or more inputs, and determining based, at least in part, on the computed metrics associated with the one or more inputs of a more inputs whether the at least one output dependent on the one or more inputs is part of a potentially malicious implementation.

2. 发明申请

US20160275288A1 DETECTION OF ANOMALOUS PROGRAM EXECUTION USING HARDWARE-BASED MICRO-ARCHITECTURAL DATA 审中-公开
标题翻译：使用基于硬件的微结构数据检测异常程序执行
公开(公告)号：US20160275288A1
公开(公告)日：2016-09-22
申请号：US14778007
申请日：2013-11-05
申请人： Lakshminarasimhan SETHUMADHAVAN , John DEMME , Jared SCHMITZ , Adrian TANG , Sal STOLFO , Matthew MAYCOCK , THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
发明人： Lakshminarasimhan SETHUMADHAVAN , John DEMME , Jared SCHMITZ , Adrian TANG , Sal STOLFO , Matthew MAYCOCK
IPC分类号： G06F21/56 , H04L9/32 , G06N99/00 , H04L29/06
CPC分类号： G06F21/566 , G06F11/3466 , G06F21/572 , G06F2201/88 , G06F2221/034 , G06N99/005 , H04L9/3239 , H04L63/0428
摘要： Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes obtaining hardware-based micro-architectural data, including hardware-based micro-architectural counter data, for a hardware device executing one or more processes, and determining based, at least in part, on the hardware-based micro-architectural data whether at least one of the one or more processes executing on the hardware device corresponds to a malicious process. In some embodiments, determining based on the hardware-based micro-architectural data whether the at least one of the one or more processes corresponds to a malicious process may include applying one or more machine-learning procedures to the hardware-based micro-architectural data to determine whether the at least one of the one or more processes corresponds to the malicious process.
摘要翻译：公开了设备，系统，装置，方法，产品，媒体和其他实施方式，包括一种方法，该方法包括获得基于硬件的微架构数据，包括基于硬件的微架构计数器数据，用于执行一个或多个进程的硬件设备以及至少部分地基于所述基于硬件的微架构数据确定在所述硬件设备上执行的所述一个或多个进程中的至少一个是否对应于恶意进程。在一些实施例中，基于基于硬件的微架构数据确定所述一个或多个进程中的至少一个是否对应于恶意进程可以包括将一个或多个机器学习过程应用于基于硬件的微架构数据以确定一个或多个进程中的至少一个是否对应于恶意进程。

3. 发明申请

US20160012228A1 IDENTIFICATION OF BACKDOORS AND BACKDOOR TRIGGERS 有权
标题翻译：背部和背部触发器的识别
公开(公告)号：US20160012228A1
公开(公告)日：2016-01-14
申请号：US14773104
申请日：2013-11-12
申请人： Lakshminarasimhan SETHUMADHAVAN , Adam WAKSMAN , Matthew SUOZZO , THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
发明人： Lakshminarasimhan SETHUMADHAVAN , Adam WAKSMAN , Matthew SUOZZO
IPC分类号： G06F21/56 , H04L29/06
CPC分类号： G06F21/566 , G06F11/263 , G06F21/56 , G06F21/71 , H04L63/1466
摘要： Disclosed are devices, systems, apparatus, methods, products, media, and other implementations, including a method that includes computing for one or more inputs of a circuit associated metrics representative of degree of influence that values of each of the one or more inputs have on at least one output dependent on the one or more inputs, and determining based, at least in part, on the computed metrics associated with the one or more inputs of a more inputs whether the at least one output dependent on the one or more inputs is part of a potentially malicious implementation.
摘要翻译：公开了设备，系统，设备，方法，产品，媒体和其他实现方式，包括一种方法，该方法包括计算代表一个或多个输入中的每一个的值的影响程度的电路的相关度量的一个或多个输入具有在至少一个输出上取决于一个或多个输入，以及至少部分地基于与多个输入的一个或多个输入相关联的所计算的度量来确定所述至少一个输出是否取决于所述一个或多个输入是潜在恶意实施的一部分。

4. 发明申请

US20130061322A1 Systems and Methods for Detecting Design-Level Attacks Against a Digital Circuit 有权
标题翻译：用于检测针对数字电路的设计级攻击的系统和方法
公开(公告)号：US20130061322A1
公开(公告)日：2013-03-07
申请号：US13580121
申请日：2011-02-28
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： G06F21/00
CPC分类号： G06F21/554 , G06F9/30145 , G06F9/3867 , G06F12/14 , G06F15/16 , G06F21/00 , G06F21/71 , G06F2221/2101
摘要： Systems and methods for detecting design-level attacks against a digital circuit which includes various functional units. A target unit is selected from among the functional units for monitoring and a predictor unit is arranged to receive events before they reach the target unit. A reactor unit is selected from among the functional units of the digital circuit which are arranged to receive events after they pass through the target unit. A monitor unit is arranged to receive predicted event messages from the predictor unit and actual event messages from the reactor unit. The monitor unit is configured to indicate an alarm based on a comparison of the predicted event messages received from the predictor unit and the actual event messages received from the reactor unit.
摘要翻译：用于检测包括各种功能单元的数字电路的设计级别攻击的系统和方法。从用于监视的功能单元中选择目标单元，并且预测单元布置成在到达目标单元之前接收事件。从数字电路的功能单元中选择反应器单元，其被布置成在它们通过目标单元之后接收事件。监视器单元布置成从预测器单元接收预测的事件消息和来自反应器单元的实际事件消息。监视器单元被配置为基于从预测器单元接收的预测事件消息与从反应器单元接收的实际事件消息的比较来指示警报。

5. 发明授权

US09325493B2 System and methods for silencing hardware backdoors 有权
公开(公告)号：US09325493B2
公开(公告)日：2016-04-26
申请号：US14671905
申请日：2015-03-27
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： H04L29/06 , G06F11/00 , G06F12/16 , G08B23/00 , H04L9/00 , G06F21/76
CPC分类号： H04L9/002 , G06F21/76 , H04L9/008 , H04L2209/16
摘要： Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.

6. 发明授权

US09037895B2 System and methods for silencing hardware backdoors 有权
标题翻译：用于消除硬件后门的系统和方法
公开(公告)号：US09037895B2
公开(公告)日：2015-05-19
申请号：US13273016
申请日：2011-10-13
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： G06F1/04 , G06F21/76
CPC分类号： H04L9/002 , G06F21/76 , H04L9/008 , H04L2209/16
摘要： Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.
摘要翻译：用于防止安装在数字电路中的硬件后门的激活的方法，所述数字电路包括要被保护的一个或多个硬件单元。定时器在小于验证时期的周期内重复启动，并且硬件单元在计时器到期时复位，以防止启动基于时间的后门。被发送到硬件单元的数据在加密元素中被加密，以使它无法识别到存在于硬件单元中的单一作弊代码硬件后门。发送到硬件单元的指令被随机地或伪随机地重新排序，使用重新排序元素确定的顺序限制来呈现嵌入在硬件单元中存在的序列作弊码硬件后门的无法识别的指令中的激活指令序列。

7. 发明申请

US20120123739A1 System and Methods for Precise Microprocessor Event Counting 有权
标题翻译：精确微处理器事件计数的系统和方法
公开(公告)号：US20120123739A1
公开(公告)日：2012-05-17
申请号：US13273035
申请日：2011-10-13
申请人： Lakshminarasimhan SETHUMADHAVAN , John D. Demme
发明人： Lakshminarasimhan SETHUMADHAVAN , John D. Demme
IPC分类号： G06F15/00
CPC分类号： G06F11/3409 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/88
摘要： Method for providing precise microprocessor performance counter readings including detecting a swap back to a monitored process executing in a microprocessor. In response to the detected swap back to the monitored process, if the value read from the performance counter does not exceed the defined overflow threshold, the value of the performance counter stored in the first memory location is restored to the performance counter. If the value read from the performance counter exceeds the defined overflow threshold, the performance counter is set to zero and the value of the performance counter stored in the first memory location is used to increment an overflow memory location. If the value read from the performance counter exceeds the defined overflow threshold, at least one performance counter reading instruction is detected and in response to the detected at least one performance counter reading instruction, setting the counter output register to zero.
摘要翻译：用于提供精确的微处理器性能计数器读数的方法，包括检测到交换回到在微处理器中执行的监视过程。响应于检测到的交换回到监视的进程，如果从性能计数器读取的值不超过定义的溢出阈值，则存储在第一存储器位置的性能计数器的值被恢复到性能计数器。如果从性能计数器读取的值超过定义的溢出阈值，则性能计数器设置为零，并且使用存储在第一存储器位置的性能计数器的值来增加溢出存储器位置。如果从性能计数器读取的值超过定义的溢出阈值，则检测至少一个性能计数器读取指令，并且响应于检测到的至少一个性能计数器读取指令，将计数器输出寄存器设置为零。

8. 发明申请

US20090013135A1 UNORDERED LOAD/STORE QUEUE 有权
标题翻译：无节奏的载入/存储队列
公开(公告)号：US20090013135A1
公开(公告)日：2009-01-08
申请号：US12166491
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/312 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/383 , G06F9/3855
摘要： A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.
摘要翻译：一种方法和处理器，用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。加载和存储指令以执行顺序插入到加载/存储队列中。加载/存储队列中的每个条目包括与程序顺序相对应的标识。可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。地址CAM和Age CAM的输出结果在逻辑上为AND。

9. 发明授权

US10025929B2 Detection of anomalous program execution using hardware-based micro-architectural data 有权
公开(公告)号：US10025929B2
公开(公告)日：2018-07-17
申请号：US14778007
申请日：2013-11-05
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , Lakshminarasimhan Sethumadhavan , John Demme , Jared Schmitz , Adrian Tang , Sal Stolfo , Matthew Maycock
发明人： Lakshminarasimhan Sethumadhavan , John Demme , Jared Schmitz , Adrian Tang , Sal Stolfo , Matthew Maycock
IPC分类号： H04L9/00 , G06F21/56 , G06F21/57 , G06N99/00 , H04L9/32 , H04L29/06 , G06F11/34
摘要： Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes obtaining hardware-based micro-architectural data, including hardware-based micro-architectural counter data, for a hardware device executing one or more processes, and determining based, at least in part, on the hardware-based micro-architectural data whether at least one of the one or more processes executing on the hardware device corresponds to a malicious process. In some embodiments, determining based on the hardware-based micro-architectural data whether the at least one of the one or more processes corresponds to a malicious process may include applying one or more machine-learning procedures to the hardware-based micro-architectural data to determine whether the at least one of the one or more processes corresponds to the malicious process.

10. 发明申请

US20160119137A1 DIVERSIFIED INSTRUCTION SET PROCESSING TO ENHANCE SECURITY 审中-公开
标题翻译：多样化指示集加工加强安全
公开(公告)号：US20160119137A1
公开(公告)日：2016-04-28
申请号：US14946961
申请日：2015-11-20
申请人： Lakshminarasimhan SETHUMADHAVAN , Kanad SINHA , Angelos KEROMYTIS , Vasilis PAPPAS , Vasileios KEMERLIS
发明人： Lakshminarasimhan SETHUMADHAVAN , Kanad SINHA , Angelos KEROMYTIS , Vasilis PAPPAS , Vasileios KEMERLIS
IPC分类号： H04L9/08 , H04L9/00 , G06F12/14
CPC分类号： H04L9/0825 , G06F9/30178 , G06F12/0897 , G06F12/1408 , G06F21/123 , G06F21/575 , G06F21/72 , G06F2212/1052 , H04L9/007
摘要： Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes receiving a block of information from non-processor memory at an interface between the non-processor memory and processor memory comprising two or more processor memory levels, determining whether the block of information received from the non-processor memory at the interface corresponds to encrypted instruction code, and decrypting the block of information at the interface between the non-processor memory and the processor memory for storage in one of the two or more levels of the processor memory in response to a determination that the received block of information corresponds to the encrypted instruction code. The block of information is stored at the one of the two or more levels of the processor memory without being decrypted when the received block of information is determined to correspond to data.
摘要翻译：公开了设备，系统，装置，方法，产品和其他实施方式，包括一种方法，其包括在非处理器存储器和处理器存储器之间的接口处从非处理器存储器接收信息块，其包括两个或多个处理器存储器级确定在接口处从非处理器存储器接收到的信息块是否对应于加密的指令代码，以及解密非处理器存储器和处理器存储器之间的接口处的信息块，以存储在两者之一或响应于确定所接收的信息块对应于加密的指令代码，处理器存储器的更多级别。当确定接收的信息块对应于数据时，信息块被存储在处理器存储器的两个或更多个级别中的一个处，而不被解密。

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