专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08447911B2 Unordered load/store queue 有权
标题翻译：无序的加载/存储队列
公开(公告)号：US08447911B2
公开(公告)日：2013-05-21
申请号：US12166491
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/383 , G06F9/3855
摘要： A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.
摘要翻译：一种方法和处理器，用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。加载和存储指令以执行顺序插入到加载/存储队列中。加载/存储队列中的每个条目包括与程序顺序相对应的标识。可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。地址CAM和Age CAM的输出结果在逻辑上为AND。

2. 发明申请

US20090013135A1 UNORDERED LOAD/STORE QUEUE 有权
标题翻译：无节奏的载入/存储队列
公开(公告)号：US20090013135A1
公开(公告)日：2009-01-08
申请号：US12166491
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/312 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/383 , G06F9/3855
摘要： A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.
摘要翻译：一种方法和处理器，用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。加载和存储指令以执行顺序插入到加载/存储队列中。加载/存储队列中的每个条目包括与程序顺序相对应的标识。可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。地址CAM和Age CAM的输出结果在逻辑上为AND。

3. 发明申请

US20100325395A1 DEPENDENCE PREDICTION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的依赖性预测
公开(公告)号：US20100325395A1
公开(公告)日：2010-12-23
申请号：US12487804
申请日：2009-06-19
申请人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example.
摘要翻译：通常描述与存储器系统的依赖性预测相关的技术。各种实现可以包括存储对应于与至少一个加载操作相关联的至少一个预测类型的值的预测器存储器和具有多个状态的状态机。例如，状态机可以基于与每个状态相关联的预测类型以及相关联的预测类型的加载操作的相应先例来确定是否执行加载操作。状态机可以基于加载操作的结果进一步确定后续加载操作的预测类型。状态机的状态例如可以对应于预测类型，其可以是保守预测类型，积极预测类型或一个或多个N-存储预测类型。

4. 发明授权

US08180997B2 Dynamically composing processor cores to form logical processors 有权
标题翻译：动态组成处理器内核以形成逻辑处理器
公开(公告)号：US08180997B2
公开(公告)日：2012-05-15
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F15/76
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

5. 发明申请

US20090013160A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 有权
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：US20090013160A1
公开(公告)日：2009-01-08
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

6. 发明申请

US20080244230A1 SCALABLE PROCESSING ARCHITECTURE 有权
标题翻译：可扩展的处理结构
公开(公告)号：US20080244230A1
公开(公告)日：2008-10-02
申请号：US12136645
申请日：2008-06-10
申请人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
发明人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

7. 发明申请

US20130086370A1 COMBINED BRANCH TARGET AND PREDICATE PREDICTION 有权
公开(公告)号：US20130086370A1
公开(公告)日：2013-04-04
申请号：US13321807
申请日：2010-06-18
申请人： Douglas C. Burger , Stephen W. Keckler
发明人： Douglas C. Burger , Stephen W. Keckler
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/30072 , G06F9/38 , G06F9/3804 , G06F9/3836 , G06F9/45516
摘要： Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

8. 发明授权

US08055881B2 Computing nodes for executing groups of instructions 有权
标题翻译：计算用于执行指令组的节点
公开(公告)号：US08055881B2
公开(公告)日：2011-11-08
申请号：US12136645
申请日：2008-06-10
申请人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
发明人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
IPC分类号： G06F15/163
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

9. 发明授权

US09021241B2 Combined branch target and predicate prediction for instruction blocks 有权
标题翻译：组合分支目标和指令块的谓词预测
公开(公告)号：US09021241B2
公开(公告)日：2015-04-28
申请号：US13321807
申请日：2010-06-18
申请人： Douglas C. Burger , Stephen W. Keckler
发明人： Douglas C. Burger , Stephen W. Keckler
IPC分类号： G06F9/38 , G06F9/455
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/30072 , G06F9/38 , G06F9/3804 , G06F9/3836 , G06F9/45516
摘要： Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.
摘要翻译：实施例提供了在使用组合分支目标和谓词预测的程序执行期间与预测谓词和分支目标相关联的方法，装置，系统和计算机可读介质。可以使用表示程序中的指令块中的谓词和块之间的分支的一个或多个预测控制流程图来进行预测。预测控制流图可以被构造为树，使得图中的每个节点与谓词指令相关联，并且每个叶与跳转到另一块的分支目标相关联。在块的执行期间，预测发生器可以采取控制点历史并产生预测。按照通过树的预测建议的路径，可以预测谓词值和分支目标。可以描述和要求保护其他实施例。

10. 发明授权

US08127119B2 Control-flow prediction using multiple independent predictors 有权
标题翻译：使用多个独立预测因子的控制流预测
公开(公告)号：US08127119B2
公开(公告)日：2012-02-28
申请号：US12329517
申请日：2008-12-05
申请人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
发明人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3848
摘要： The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
摘要翻译：本公开通常描述具有包括一个或多个分支预测器布置的多核处理器的计算系统。分支预测器被配置为预测与其相关联的并且将在计算系统的至少一个处理器核心上执行的单个和完整的程序指令流。通过描述的方法可以改善整体处理器性能和物理可扩展性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式