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1. 发明授权

US08122334B2 Parity error detecting circuit and method 有权
标题翻译：奇偶校验误差检测电路及方法
公开(公告)号：US08122334B2
公开(公告)日：2012-02-21
申请号：US11829583
申请日：2007-07-27
申请人： Young-Hun Lee , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
发明人： Young-Hun Lee , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
IPC分类号： G06F11/10 , G06F11/28
CPC分类号： H04L1/0061
摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.
摘要翻译：奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。移位寄存器响应于第一时钟信号移位第一信号并输出第二信号。第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

2. 发明申请

US20070018686A1 Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver 失效
标题翻译：低电压差分信号接收器和校准低电压差分信号接收器的终端电阻的方法
公开(公告)号：US20070018686A1
公开(公告)日：2007-01-25
申请号：US11434960
申请日：2006-05-16
申请人： Jae-Suk Yu , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
发明人： Jae-Suk Yu , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
IPC分类号： H03K19/094
CPC分类号： H04L25/0298 , H04L25/0278
摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.
摘要翻译：低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并且响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压，基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。还公开了相应的方法。

3. 发明授权

US07106095B2 Circuit for compensating for the declination of balanced impedance elements and a frequency mixer 有权
标题翻译：用于补偿平衡阻抗元件偏移的电路和混频器
公开(公告)号：US07106095B2
公开(公告)日：2006-09-12
申请号：US10858240
申请日：2004-06-01
申请人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
发明人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
IPC分类号： H03K19/003
CPC分类号： H03D7/145 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0047 , H03D2200/0088 , H04B1/30
摘要： Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.
摘要翻译：提供了用于补偿平衡阻抗元件的偏角的电路和混频器。补偿电路补偿在第一和第二阻抗元件处测量的阻抗之间的差异，并且包括第一和第二阻抗电路。响应于具有k位的控制信号的n个较低位，第一阻抗电路将第一阻抗值变换成具有2阶段的精细阻抗值。第二阻抗电路响应于控制信号的m个高位将第二阻抗值变换成具有2μs步长的粗阻抗值。第一和第二阻抗值分别在第一和第二阻抗元件处测量，并且k等于m加n。阻抗元件之间的阻抗差是线性调节的。

4. 发明授权

US07332933B2 Circuit for compensating for the declination of balanced impedance elements and a frequency mixer 有权
标题翻译：用于补偿平衡阻抗元件偏移的电路和混频器
公开(公告)号：US07332933B2
公开(公告)日：2008-02-19
申请号：US11496145
申请日：2006-07-31
申请人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
发明人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03D7/145 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0047 , H03D2200/0088 , H04B1/30
摘要： Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.
摘要翻译：提供了用于补偿平衡阻抗元件的偏角的电路和混频器。补偿电路补偿在第一和第二阻抗元件处测量的阻抗之间的差异，并且包括第一和第二阻抗电路。响应于具有k位的控制信号的n个较低位，第一阻抗电路将第一阻抗值变换成具有2阶段的精细阻抗值。第二阻抗电路响应于控制信号的m个高位将第二阻抗值变换成具有2μs步长的粗阻抗值。第一和第二阻抗值分别在第一和第二阻抗元件处测量，并且k等于m加n。阻抗元件之间的阻抗差是线性调节的。

5. 发明申请

US20060261845A1 Circuit for compensating for the declination of balanced impedance elements and a frequency mixer 有权
公开(公告)号：US20060261845A1
公开(公告)日：2006-11-23
申请号：US11496145
申请日：2006-07-31
申请人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
发明人： Young-Jin Kim , Kyung-Suc Nah , In-Chul Hwang , Young-Suk Son
IPC分类号： H03K19/003
CPC分类号： H03D7/145 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0047 , H03D2200/0088 , H04B1/30
摘要： Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

6. 发明申请

US20080168338A1 PARITY ERROR DETECTING CIRCUIT AND METHOD 有权
标题翻译：奇偶校验错误检测电路和方法
公开(公告)号：US20080168338A1
公开(公告)日：2008-07-10
申请号：US11829583
申请日：2007-07-27
申请人： Young-Hun Lee , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
发明人： Young-Hun Lee , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
IPC分类号： G06F11/10
CPC分类号： H04L1/0061
摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.
摘要翻译：奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。移位寄存器响应于第一时钟信号移位第一信号并输出第二信号。第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

7. 发明授权

US06424228B1 Stabilized phase lock detection circuits and methods of operation therefor 失效
标题翻译：稳定锁相检测电路及其操作方法
公开(公告)号：US06424228B1
公开(公告)日：2002-07-23
申请号：US09665936
申请日：2000-09-20
申请人： Tae-won Ahn , Kyung-suc Nah
发明人： Tae-won Ahn , Kyung-suc Nah
IPC分类号： H03L7095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.
摘要翻译：锁相检测电路包括相位检测电路，该相位检测电路响应于第一输入信号和施加到其的第二输入信号产生具有第一逻辑状态或第二逻辑状态之一的相位检测信号。稳定的锁相指示电路电耦合到相位检测电路，并产生具有第一逻辑状态或第二逻辑状态之一的锁相指示信号，锁相指示信号改变为其第一和第二逻辑响应于相位检测信号在其第一和第二逻辑状态中的相应一个中保持预定时间间隔的状态。在第一实施例中，通过监视数字计数来控制锁相指示。在第二实施例中，通过监视电容器电压来控制锁相指示信号。还讨论了相关的操作方法。

8. 发明授权

US07315185B2 Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver 失效
标题翻译：低电压差分信号接收器和校准低电压差分信号接收器的终端电阻的方法
公开(公告)号：US07315185B2
公开(公告)日：2008-01-01
申请号：US11434960
申请日：2006-05-16
申请人： Jae-Suk Yu , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
发明人： Jae-Suk Yu , Jae-Youl Lee , Jong-Seon Kim , Kyung-Suc Nah
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H04L25/0278
摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.
摘要翻译：低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压，基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。还公开了相应的方法。

9. 发明授权

US06177842B1 Stabilized phase lock detection circuits and methods of operation therefor 失效
标题翻译：稳定锁相检测电路及其操作方法
公开(公告)号：US06177842B1
公开(公告)日：2001-01-23
申请号：US09170938
申请日：1998-10-13
申请人： Tae-won Ahn , Kyung-suc Nah
发明人： Tae-won Ahn , Kyung-suc Nah
IPC分类号： H03L7095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.
摘要翻译：锁相检测电路包括相位检测电路，该相位检测电路响应于第一输入信号和施加到其的第二输入信号产生具有第一逻辑状态或第二逻辑状态之一的相位检测信号。稳定的锁相指示电路电耦合到相位检测电路，并产生具有第一逻辑状态或第二逻辑状态之一的锁相指示信号，锁相指示信号改变为其第一和第二逻辑响应于相位检测信号在其第一和第二逻辑状态中的相应一个中保持预定时间间隔的状态。在第一实施例中，通过监视数字计数来控制锁相指示。在第二实施例中，通过监视电容器电压来控制锁相指示信号。还讨论了相关的操作方法。

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