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1. 发明申请

US20120108070A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US20120108070A1
公开(公告)日：2012-05-03
申请号：US13191525
申请日：2011-07-27
申请人： Kyung Ae KIM
发明人： Kyung Ae KIM
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76229 , H01L27/105 , H01L27/1052
摘要： A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first hard mask layer over a semiconductor substrate including a cell region and a peripheral circuit region, forming a spacer pattern over the first hard mask layer of the cell region, forming a cell-open mask pattern over the peripheral circuit region, forming a first hard mask pattern by etching the first hard mask layer using the spacer pattern of the cell region as an etch mask, forming a second hard mask layer over the first hard mask pattern of the cell region and a first hard mask layer of the peripheral circuit region, forming a cutting mask pattern over the second hard mask layer; and forming an active region in the cell region and a device isolation region in the peripheral circuit region by etching the second hard mask layer, the first hard mask pattern of the cell region, the first hard mask layer of the peripheral circuit region, and the semiconductor substrate using the cutting mask pattern as an etch mask.
摘要翻译：公开了一种用于形成半导体器件的方法。一种形成半导体器件的方法包括：在包括单元区域和外围电路区域的半导体衬底上形成第一硬掩模层，在所述单元区域的第一硬掩模层上形成间隔物图案，形成电池开放掩模图案通过在外围电路区域上形成第一硬掩模图案，通过使用单元区域的间隔图案作为蚀刻掩模蚀刻第一硬掩模层，在单元区域的第一硬掩模图案之上形成第二硬掩模层，以及所述外围电路区域的第一硬掩模层，在所述第二硬掩模层上形成切割掩模图案; 以及通过蚀刻第二硬掩模层，单元区域的第一硬掩模图案，外围电路区域的第一硬掩模层和外围电路区域的第一硬掩模层，在周边电路区域中形成有源区域和外围电路区域中的器件隔离区域使用切割掩模图案作为蚀刻掩模的半导体基板。

2. 发明授权

US6093836A 1,3-diphenylpropane derivatives having inhibitory activity against tyrosinase and process for preparation thereof 失效
标题翻译：对酪氨酸酶具有抑制活性的1,3-二苯基丙烷衍生物及其制备方法
公开(公告)号：US6093836A
公开(公告)日：2000-07-25
申请号：US180352
申请日：1998-11-06
申请人： Young Ho Rhee , Kyung Ae Kim , Hyun Ho Lee , Jong Kwon Choi , Sang Hwa Lee
发明人： Young Ho Rhee , Kyung Ae Kim , Hyun Ho Lee , Jong Kwon Choi , Sang Hwa Lee
IPC分类号： C07D311/72 , A61K8/00 , A61K8/33 , A61Q19/00 , C07C37/055 , C07C39/12 , C07C39/15 , C07C41/26 , C07C43/23 , C07C45/62 , C07C45/74 , C07C49/83 , C07C49/84 , C07D311/58 , C07C43/205 , C07C49/303 , C07C49/603
CPC分类号： C07D311/58 , C07C39/12 , C07C39/15 , C07C43/23 , C07C45/74 , C07C49/84
摘要： The present invention relates to a novel 1,3-diphenylpropane derivative having an inhibitory activity against tyrosinase represented by the following formula (I): ##STR1## in which - - represents double or single bond,R.sub.1 represents hydrogen or C.sub.1 -C.sub.10 alkyl,R.sub.2 represents C.sub.1 -C.sub.5 alkyl or C.sub.1 -C.sub.5 alkoxyalkyl, orR.sub.1 and R.sub.2 together represent a 5 to 6 membered heterocycle which can be substituted by C.sub.1 -C.sub.5 alkyl and which contains oxygen as the hetero atom,R.sub.3 represents hydrogen or C.sub.1 -C.sub.7 alkyl,R.sub.4 represents hydrogen, hydroxy, or oxo, andR.sub.5 and R.sub.6 mindependently of one another represent hydrogen or C.sub.1 -C.sub.5 alkyl.
摘要翻译： PCT No.PCT / KR98 / 00039 Sec。 371日期：1998年11月6日 102（e）日期1998年11月6日PCT 1998年3月2日PCT公布。公开号WO98 / 39279 日期：1998年9月11日本发明涉及对下述式（I）表示的酪氨酸酶具有抑制活性的新型1,3-二苯基丙烷衍生物：其中+ E，uns - + EE表示双键或单键，R1 表示氢或C 1 -C 10烷基，R 2表示C 1 -C 5烷基或C 1 -C 5烷氧基烷基，或者R 1和R 2一起表示可被C 1 -C 5烷基取代并含有氧作为杂原子的5至6元杂环， R 3表示氢或C 1 -C 7烷基，R 4表示氢，羟基或氧代，且R 5和R 6彼此独立地表示氢或C 1 -C 5烷基。

3. 发明申请

US20150254458A1 ELECTRONIC SYSTEM HAVING INTEGRITY VERIFICATION DEVICE 有权
标题翻译：具有完整性验证装置的电子系统
公开(公告)号：US20150254458A1
公开(公告)日：2015-09-10
申请号：US14638862
申请日：2015-03-04
申请人： Tong-Pyo HONG , Kyung-Ae KIM , Jae-Chul PARK , Yun-Ho YOUM , Heon-Soo LEE , Hye-Soo LEE
发明人： Tong-Pyo HONG , Kyung-Ae KIM , Jae-Chul PARK , Yun-Ho YOUM , Heon-Soo LEE , Hye-Soo LEE
IPC分类号： G06F21/57
CPC分类号： G06F21/57 , G06F21/64 , G06F21/79 , G06F2221/034 , G06F2221/2139
摘要： Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.
摘要翻译：提供电子系统，完整性验证装置和执行完整性验证操作的方法。电子系统包括：存储装置; 处理器，其被配置为提供与存储在所述存储器件中的多个验证数据相对应的多个配置记录，所述配置记录包括相应验证数据的起始地址，数据长度和参考散列值; 以及完整性验证装置，被配置为：基于包括在所选配置记录中的开始地址和数据长度，存储配置记录，选择配置记录，直接访问存储设备以读取与所选配置记录相对应的验证数据对验证数据执行哈希操作以获得验证散列值，并且基于所选配置记录中包含的验证散列值和参考散列值输出中断信号。

4. 发明授权

US08426314B2 Method for forming semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US08426314B2
公开(公告)日：2013-04-23
申请号：US13191525
申请日：2011-07-27
申请人： Kyung Ae Kim
发明人： Kyung Ae Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76229 , H01L27/105 , H01L27/1052
摘要： A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first hard mask layer over a semiconductor substrate including a cell region and a peripheral circuit region, forming a spacer pattern over the first hard mask layer of the cell region, forming a cell-open mask pattern over the peripheral circuit region, forming a first hard mask pattern by etching the first hard mask layer using the spacer pattern of the cell region as an etch mask, forming a second hard mask layer over the first hard mask pattern of the cell region and a first hard mask layer of the peripheral circuit region, forming a cutting mask pattern over the second hard mask layer; and forming an active region in the cell region and a device isolation region in the peripheral circuit region by etching the second hard mask layer, the first hard mask pattern of the cell region, the first hard mask layer of the peripheral circuit region, and the semiconductor substrate using the cutting mask pattern as an etch mask.
摘要翻译：公开了一种用于形成半导体器件的方法。一种形成半导体器件的方法包括：在包括单元区域和外围电路区域的半导体衬底上形成第一硬掩模层，在所述单元区域的第一硬掩模层上形成间隔物图案，形成电池开放掩模图案通过在外围电路区域上形成第一硬掩模图案，通过使用单元区域的间隔图案作为蚀刻掩模蚀刻第一硬掩模层，在单元区域的第一硬掩模图案之上形成第二硬掩模层，以及所述外围电路区域的第一硬掩模层，在所述第二硬掩模层上形成切割掩模图案; 以及通过蚀刻第二硬掩模层，单元区域的第一硬掩模图案，外围电路区域的第一硬掩模层和外围电路区域的第一硬掩模层，在外围电路区域中形成有源区域和外围电路区域中的器件隔离区域使用切割掩模图案作为蚀刻掩模的半导体基板。

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