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1. 发明授权

US09798849B2 Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems 有权
公开(公告)号：US09798849B2
公开(公告)日：2017-10-24
申请号：US14688440
申请日：2015-04-16
申请人： Jae-Pil Shin , Chang-Woo Kang , Jong-Won Kim , Ho-Joon Lee , Kyu-Baik Chang , Won-Young Chung
发明人： Jae-Pil Shin , Chang-Woo Kang , Jong-Won Kim , Ho-Joon Lee , Kyu-Baik Chang , Won-Young Chung
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009
摘要： A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

2. 发明申请

US20060272561A1 Deposition apparatus 审中-公开
标题翻译：沉积装置
公开(公告)号：US20060272561A1
公开(公告)日：2006-12-07
申请号：US11445346
申请日：2006-06-02
申请人： Kyu-Baik Chang , Tai-Kyung Kim , Jae-Hyun Han , Won-Young Chung , Hyung-Kyu Kim
发明人： Kyu-Baik Chang , Tai-Kyung Kim , Jae-Hyun Han , Won-Young Chung , Hyung-Kyu Kim
IPC分类号： A01C7/00 , A01C9/00
CPC分类号： H01L21/68735 , H01L21/68721
摘要： A deposition apparatus may include a deposition-preventing member for preventing deposition of process gas on a portion of substrate removeably arranged inside a processing chamber. The deposition-preventing member may include a fixing member for fixing the deposition preventing member to a fixed body of the processing chamber, a blocking member for blocking the to-be-blocked portion of the substrate to be processed, and a guiding member for guiding fluid and particles out from the processing chamber, the guiding member may include a guiding surface that prevents a vortex from forming on the deposition-preventing member when fluid and particles are flowing out of the processing chamber.
摘要翻译：沉积设备可以包括用于防止处理气体沉积在可移除地布置在处理室内的基板的一部分上的防沉积构件。防沉积构件可以包括用于将防沉积构件固定到处理室的固定体的固定构件，用于阻挡待处理基板的待封闭部分的阻挡构件和用于引导流体和颗粒从处理室排出，引导构件可以包括引导表面，当引导流体和颗粒流出处理室时，引导表面防止在防沉积构件上形成涡流。

3. 发明授权

US09698154B2 Semiconductor device 有权
公开(公告)号：US09698154B2
公开(公告)日：2017-07-04
申请号：US15168349
申请日：2016-05-31
申请人： Joon Sung Lim , Kyu Baik Chang , Sung Hoi Hur , Woo Jung Kim
发明人： Joon Sung Lim , Kyu Baik Chang , Sung Hoi Hur , Woo Jung Kim
IPC分类号： H01L21/764 , H01L27/115 , H01L27/11575 , H01L27/1157 , H01L27/11573 , H01L21/8238 , H01L21/8234
CPC分类号： H01L27/11575 , H01L21/823481 , H01L21/823878 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00
摘要： A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.

4. 发明申请

US20160163730A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160163730A1
公开(公告)日：2016-06-09
申请号：US14959209
申请日：2015-12-04
申请人： JOON-SUNG LIM , JANG-GN YUN , SUNGHOON BAE , JAESUN YUN , KYU-BAIK CHANG
发明人： JOON-SUNG LIM , JANG-GN YUN , SUNGHOON BAE , JAESUN YUN , KYU-BAIK CHANG
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
摘要翻译：半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

5. 发明申请

US20160012174A1 METHODS OF DETECTING STRESSES, METHODS OF TRAINING COMPACT MODELS, METHODS OF RELAXING STRESSES, AND COMPUTING SYSTEMS 有权
标题翻译：检测应力的方法，训练紧凑型模型的方法，放松应力的方法和计算系统
公开(公告)号：US20160012174A1
公开(公告)日：2016-01-14
申请号：US14688440
申请日：2015-04-16
申请人： Jae-Pil SHIN , Chang-Woo KANG , Jong-Won KIM , Ho-Joon LEE , Kyu-Baik CHANG , Won-Young CHUNG
发明人： Jae-Pil SHIN , Chang-Woo KANG , Jong-Won KIM , Ho-Joon LEE , Kyu-Baik CHANG , Won-Young CHUNG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009
摘要： A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.
摘要翻译：检测包括由不同材料形成的第一和第二图案的集成电路的应力的方法可以包括：确定第一图案的一个或多个应力检测点; 将包含所述一个以上应力检测点的第一应力检测点的区域划分为多个分割区域; 计算分割区域的第二模式的面积; 和/或基于分割区域处的第二图案的区域来检测施加到第一图案的第一应力检测点的应力水平的第二图案。

6. 发明申请

US20100114553A1 Systems and Methods for Executing Unified Process-Device-Circuit Simulation 有权
标题翻译：执行统一过程设备电路仿真的系统和方法
公开(公告)号：US20100114553A1
公开(公告)日：2010-05-06
申请号：US12607206
申请日：2009-10-28
申请人： Kyung Rok Kim , Kyu-Baik Chang , Young Kwan Park , Seung Chul Lee , Jin Kyu Park
发明人： Kyung Rok Kim , Kyu-Baik Chang , Young Kwan Park , Seung Chul Lee , Jin Kyu Park
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5022 , G06F11/3476 , G06F13/105 , G06F17/5009
摘要： A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
摘要翻译：提供统一的仿真系统。该统一模拟系统包括存储包括输入参数和环境信息的输入数据的输入数据库，统一模拟器，根据输入数据和至少一个预定模型，对半导体装置的特性执行统一的处理装置电路仿真，并输出作为输出数据的模拟结果，以及存储输出数据的输出数据库。统一模拟器包括：基于输入数据模拟至少一个过程并输出过程特征数据的过程仿真器;基于过程特性数据模拟至少一个设备并输出设备特征数据的设备模拟器;以及模拟电路的电路仿真器包括所述至少一个装置。因此，可以同时优化多个装置以优化电路特性，并且可以提供在处理和设备级别的精确规格。

7. 发明申请

US20070087529A1 Simulation method of wafer warpage 审中-公开
标题翻译：晶圆翘曲的仿真方法
公开(公告)号：US20070087529A1
公开(公告)日：2007-04-19
申请号：US11580352
申请日：2006-10-13
申请人： Won-Young Chung , Tai-Kyung Kim , Young-Kwan Park , Ui-Hui Kwon , Kyu-Baik Chang
发明人： Won-Young Chung , Tai-Kyung Kim , Young-Kwan Park , Ui-Hui Kwon , Kyu-Baik Chang
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76838
摘要： Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a plurality of unit layer, and utilizes values of mechanical characteristics, which are obtained from the transformed layer structure, for estimating wafer warpage. As a result, it is possible to complete an operation of wafer warpage simulation using information about pattern density of the semiconductor device.
摘要翻译：公开了一种用于确定晶片翘曲的模拟方法。该方法包括分层和评估构成层的材料的组成比。该方法将构成为具有各种材料的复杂结构的半导体器件数学地变换为包括多个单位层的简化的，数学上等效的堆叠结构，并利用从变换层结构获得的机械特性值，用于估计晶片翘曲。结果，可以使用关于半导体器件的图案密度的信息来完成晶片翘曲模拟的操作。

8. 发明申请

US20170040335A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20170040335A1
公开(公告)日：2017-02-09
申请号：US15168349
申请日：2016-05-31
申请人： Joon Sung LIM , Kyu Baik CHANG , Sung Hoi HUR , Woo Jung KIM
发明人： Joon Sung LIM , Kyu Baik CHANG , Sung Hoi HUR , Woo Jung KIM
IPC分类号： H01L27/115
CPC分类号： H01L27/11575 , H01L21/823481 , H01L21/823878 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00
摘要： A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.
摘要翻译：半导体器件包括衬底，多个存储单元阵列和气隙结构。基板包括单元区域，外围电路区域和边界区域。边界区域在单元区域和外围电路区域之间。多个存储单元阵列位于单元区域上。气隙结构包括形成在基板的边界区域中的沟槽。气隙结构限定气隙。

9. 发明授权

US09548316B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09548316B2
公开(公告)日：2017-01-17
申请号：US14959209
申请日：2015-12-04
申请人： Joon-Sung Lim , Jang-Gn Yun , Sunghoon Bae , Jaesun Yun , Kyu-Baik Chang
发明人： Joon-Sung Lim , Jang-Gn Yun , Sunghoon Bae , Jaesun Yun , Kyu-Baik Chang
IPC分类号： H01L27/12 , H01L27/115 , H01L27/06
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11575
摘要： A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
摘要翻译：半导体器件包括逻辑结构，该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体，逻辑结构上的存储器结构，插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构以及连接结构，其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

10. 发明授权

US09235664B2 Systems and methods for executing unified process-device-circuit simulation 有权
标题翻译：执行统一过程设备电路仿真的系统和方法
公开(公告)号：US09235664B2
公开(公告)日：2016-01-12
申请号：US12607206
申请日：2009-10-28
申请人： Kyung Rok Kim , Kyu-Baik Chang , Young Kwan Park , Seung Chul Lee , Jin Kyu Park
发明人： Kyung Rok Kim , Kyu-Baik Chang , Young Kwan Park , Seung Chul Lee , Jin Kyu Park
IPC分类号： G06F17/50 , G06G7/62 , G06F9/44 , G06F13/10 , G06F13/12 , G06F11/34
CPC分类号： G06F17/5022 , G06F11/3476 , G06F13/105 , G06F17/5009
摘要： A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
摘要翻译：提供统一的仿真系统。该统一模拟系统包括存储包括输入参数和环境信息的输入数据的输入数据库，统一模拟器，根据输入数据和至少一个预定模型，对半导体装置的特性执行统一的处理装置电路仿真，并输出作为输出数据的模拟结果，以及存储输出数据的输出数据库。统一模拟器包括：基于输入数据模拟至少一个过程并输出过程特征数据的过程仿真器;基于过程特性数据模拟至少一个设备并输出设备特征数据的设备模拟器;以及模拟电路的电路仿真器包括所述至少一个装置。因此，可以同时优化多个装置以优化电路特性，并且可以提供在处理和设备级别的精确规格。

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