专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080023335A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND PLATING APPARATUS 有权
标题翻译：制造半导体器件的方法和镀膜设备
公开(公告)号：US20080023335A1
公开(公告)日：2008-01-31
申请号：US11829129
申请日：2007-07-27
申请人： Koji ARITA , Ryohei KITAO
发明人： Koji ARITA , Ryohei KITAO
IPC分类号： C25D7/12 , C25D17/00 , C25D21/12 , C25D5/00
CPC分类号： C25D21/12 , H01L21/2885 , H01L21/76877
摘要： A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr═S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.
摘要翻译：制造本发明的半导体器件的方法包括：用导电材料填充设置在形成在基板上的绝缘膜的多个凹槽的电镀工艺，其中所述电镀工艺包括执行步骤（S104）的工艺步骤（S104）通过基于第一表面积S的表面积Sr-S 1/2的比例来校正预定的第一参考电流密度而获得的第一电流密度的电镀在衬底的整个表面上，包括在半导体衬底的整个表面上的多个凹槽的侧壁的面积，以及第二表面区域2＆lt; 2＆gt; 在不包括多个凹部的侧壁的区域的基板的整个表面上，当在多个凹部的所有凹部中的不大于预定宽度的细小凹部填充有导电材料时。

IPRDB

热门服务

关于我们

友情链接

联系方式