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1. 发明申请

US20060046316A1 Method of producing ferroelectric capacitor 失效
公开(公告)号：US20060046316A1
公开(公告)日：2006-03-02
申请号：US11105505
申请日：2005-04-14
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： H01L21/8242
CPC分类号： H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L28/55
摘要： A method of producing a ferroelectric capacitor includes forming a first insulating layer on a semiconductor substrate with an MOSFET. After a first interlayer insulating layer is formed, a first conductive layer, a ferroelectric layer, and a second conductive layer are laminated on the first interlayer insulating layer to form a ferroelectric capacitor. After a first opening is formed in a ferroelectric thin layer, first restoration annealing is performed relative to a first member formed of a first interlayer insulating layer and the ferroelectric capacitor. A second interlayer insulating layer is formed on the first interlayer insulating layer, and a second opening is formed in the second interlayer insulating layer through etching. Then, second restoration annealing is performed relative to a second member formed of the first member and the second interlayer insulating layer with the second opening under in an order of nitrogen, oxygen, and nitrogen, respectively.

2. 发明授权

US07579640B2 Hybrid memory device 失效
标题翻译：混合存储设备
公开(公告)号：US07579640B2
公开(公告)日：2009-08-25
申请号：US11228188
申请日：2005-09-19
申请人： Yoko Kajita , Ichiro Koiwa , Takao Kanehara , Kinya Ashikaga , Kazuhide Abe
发明人： Yoko Kajita , Ichiro Koiwa , Takao Kanehara , Kinya Ashikaga , Kazuhide Abe
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , H01L21/76834 , H01L21/76838 , H01L27/11507
摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.
摘要翻译：一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

3. 发明申请

US20050098810A1 Semiconductor memory devices and methods of fabricating semiconductor memory device 失效
标题翻译：半导体存储器件及半导体存储器件的制造方法
公开(公告)号：US20050098810A1
公开(公告)日：2005-05-12
申请号：US10761222
申请日：2004-01-22
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： G11C11/22 , G11C5/06 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/76
CPC分类号： G11C11/22 , H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device includes a plate line driving portion having a control transistor connected to a plate line, a selection transistor in which a control electrode is connected to a word line and one end of a main current path is connected to a bit line, a ferroelectric capacitor connected to the other end of the main path of the selection transistor and the plate line, a first power supply connected to a sense amplifier and a precharge circuit, and a second power supply connected to a plate line driving portion, disposed as a separate system from the first power supply and insulated at the time of non-operation from the first power supply. The selection transistor is formed in a first semiconductor region and a main current path of the control transistor is formed in a second semiconductor region that is insulated through insulating films from the first region.
摘要翻译：一种半导体存储器件，包括具有连接到板极线的控制晶体管的板线驱动部分，其中控制电极连接到字线并且主电流通路的一端连接到位线的选择晶体管，连接到选择晶体管和板线的主路径的另一端的铁电电容器，连接到读出放大器和预充电电路的第一电源，以及连接到板线驱动部分的第二电源，设置为与第一电源分开的系统与第一电源不工作时绝缘。选择晶体管形成在第一半导体区域中，并且控制晶体管的主电流路径形成在通过绝缘膜与第一区域绝缘的第二半导体区域中。

4. 发明授权

US06781866B2 Semiconductor memory and writing method and reading method for the same 失效
标题翻译：半导体存储器和写入方法及读取方法相同
公开(公告)号：US06781866B2
公开(公告)日：2004-08-24
申请号：US10654904
申请日：2003-09-05
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A semiconductor memory includes bit lines, memory cells and a sense amplifier both of which are connected to the bit lines. Each of the memory cells includes a transistor and a capacitor. The capacitor is made of a material having a quantity of residual dielectric polarization in an electroless state in a hysteresis characteristic that is not reduced to less than a threshold value until after a lapse of a time of a refreshing cycle. The refresh cycle includes clock cycles. The sense amplifier detects an output current on the bit lines due to the residual dielectric polarization. The sense amplifier amplifies the output current to refresh the quantity of residual dielectric polarization of the capacitor when the detected level is equal to or larger than the threshold value. The sense amplifier does not amplify the output current when the detected level is less than the threshold value.
摘要翻译：半导体存储器包括位线，存储单元和读出放大器，两者均连接到位线。每个存储单元包括晶体管和电容器。电容器由具有一定量的残留电介质极化的材料制成，其具有在滞后特性中的无电化状态，直到经过刷新周期的时间之后，其不降低到小于阈值。刷新周期包括时钟周期。读出放大器由于残留的电介质极化而检测位线上的输出电流。当检测到的电平等于或大于阈值时，读出放大器放大输出电流以刷新电容器的残余介电极化量。当检测到的电平小于阈值时，读出放大器不会放大输出电流。

5. 发明授权

US07232693B2 Method for manufacturing ferroelectric memory 有权
标题翻译：铁电存储器的制造方法
公开(公告)号：US07232693B2
公开(公告)日：2007-06-19
申请号：US11102809
申请日：2005-04-11
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： H01L21/00 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/11507 , H01L27/11502 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate formed with a MOSFET is prepared, and a first interlayer insulating film is deposited on the semiconductor substrate. A ferroelectric capacitor is formed on the first interlayer insulating film. Next, a second interlayer insulating film is formed on a first structure provided with the semiconductor substrate, the first interlayer insulating film and the ferroelectric capacitor so as to embed the ferroelectric capacitor therein. Openings for electrically connecting the MOSFET and the ferroelectric capacitor and an external circuit of a ferroelectric memory are formed in the second interlayer insulating film to form a second structure. A metal wiring is formed on the second interlayer insulating film to form a third structure. Next, the third structure is heat-treated in an atmosphere from over 350° C. to under 450° C.
摘要翻译：制备由MOSFET形成的半导体衬底，并且在半导体衬底上沉积第一层间绝缘膜。在第一层间绝缘膜上形成铁电电容器。接下来，在设置有半导体衬底，第一层间绝缘膜和铁电电容器的第一结构上形成第二层间绝缘膜，以便将铁电电容器嵌入其中。用于电连接MOSFET和铁电电容器的开口和铁电存储器的外部电路形成在第二层间绝缘膜中以形成第二结构。金属布线形成在第二层间绝缘膜上以形成第三结构。接下来，将第三结构在350℃以上至450℃以下的气氛中进行热处理。

6. 发明申请

US20060240577A1 Ferroelectric capacitor and manufacturing method thereof 审中-公开
标题翻译：铁电电容器及其制造方法
公开(公告)号：US20060240577A1
公开(公告)日：2006-10-26
申请号：US11393743
申请日：2006-03-31
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： H01L21/00
CPC分类号： H01L28/55 , H01L27/11502
摘要： The present invention provides a method for manufacturing a ferroelectric capacitor, comprising the steps of sequentially forming a first conductive film on a semiconductor substrate, a ferroelectric film on the first conductive film, and a second conductive film on the ferroelectric film respectively; etching the second conductive film to form an upper electrode; patterning a resist film after formation of the resist film on the upper electrode; batch-etching the ferroelectric film and the first conductive film with the resist film as a mask to form a lower electrode from the first conductive film; and allowing a tapered angle formed between a bottom face and a sidewall portion of each of the lower electrode and the ferroelectric film to range from 30° to 40°.
摘要翻译：本发明提供一种强电介质电容器的制造方法，其特征在于，具有以下步骤：在所述第一导电膜上依次形成第一导电膜，在所述第一导电膜上形成铁电膜，在所述强电介质膜上分别形成第二导电膜; 蚀刻第二导电膜以形成上电极; 在上电极上形成抗蚀剂膜之后形成抗蚀剂膜; 用抗蚀剂膜作为掩模对铁电体膜和第一导电膜进行分批蚀刻，从第一导电膜形成下电极; 并且允许在下电极和铁电体膜中的每一个的底面和侧壁部分之间形成的锥形角度范围为30°至40°。

7. 发明申请

US20060065917A1 Hybrid memory device and method for manufacturing the same 失效
标题翻译：混合存储装置及其制造方法
公开(公告)号：US20060065917A1
公开(公告)日：2006-03-30
申请号：US11228188
申请日：2005-09-19
申请人： Yoko Kajita , Ichiro Koiwa , Takao Kanehara , Kinya Ashikaga , Kazuhide Abe
发明人： Yoko Kajita , Ichiro Koiwa , Takao Kanehara , Kinya Ashikaga , Kazuhide Abe
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L21/76834 , H01L21/76838 , H01L27/11507
摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.
摘要翻译：一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

8. 发明授权

US06501674B2 Semiconductor memory and its driving method 有权
标题翻译：半导体存储器及其驱动方法
公开(公告)号：US06501674B2
公开(公告)日：2002-12-31
申请号：US09943513
申请日：2001-08-31
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.
摘要翻译： 1T / 1C型铁电存储器具有一对虚拟存储单元DMC2n-1和DMC2n。不同的信息已被存储在虚拟存储器单元中。当从每个虚拟存储单元读出信息时，在位线BL2n-1上形成电位Va，在相邻位线BL2n上形成电位Vb。由于位线BL2n-1和BL2n具有相同的电容，所以由短路部分s2a短路的每个位线的电位Vave等于电位的正好中间值（Va + Vb）/ 2 Va和Vb。电位Vave被应用于读出放大器SAn-1和SAn作为参考电位。

9. 发明授权

US06411540B1 Ferroelectric random access memory and its operating method 失效
标题翻译：铁电随机存取存储器及其操作方法
公开(公告)号：US06411540B1
公开(公告)日：2002-06-25
申请号：US09644047
申请日：2000-08-23
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device in which an imprint is prevented, and a method of operating the ferroelectric memory device to prevent its characteristics from deteriorating due to an imprint. The ferroelectric memory device includes a sense amplifier having first and second transistors which connect first and third sub-bit lines to a ground in accordance with a sense amplifier control signal, third and fourth transistors which connect the first sub-bit line with a fourth sub-bit line and further connect the third sub-bit line with a second sub-bit line in accordance with a first switching control signal, and fifth and sixth transistors which connect the first sub-bit line with the second sub-bit line and further connect the third sub-bit line with the fourth sub-bit line in accordance with a second switching control signal.
摘要翻译：防止压印的铁电存储器件，以及操作铁电存储器件以防止其特性由于印记而劣化的方法。铁电存储器件包括读出放大器，其具有根据读出放大器控制信号将第一和第三子位线连接到地的第一和第二晶体管，将第一子位线与第四子串连接的第三和第四晶体管并且根据第一开关控制信号进一步将第三子位线与第二子位线连接，以及将第一子位线与第二子位线连接的第五和第六晶体管，根据第二切换控制信号将第三子位线与第四子位线连接。

10. 发明申请

US20090267727A1 Thin film resistor element and manufacturing method of the same 有权
标题翻译：薄膜电阻元件及其制造方法相同
公开(公告)号：US20090267727A1
公开(公告)日：2009-10-29
申请号：US12382894
申请日：2009-03-26
申请人： Kinya Ashikaga
发明人： Kinya Ashikaga
IPC分类号： H01C1/012 , H01C17/06
CPC分类号： H01C1/012 , H01C1/032 , H01C17/065 , Y10T29/49099
摘要： In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate 10 including an integrated circuit 12 having a plurality of electrode pads 14 placed in a distance from each other in the most upper part of a plurality of stacked interconnections, and the integrated circuit 12 having a passivation film 16 formed between the plurality of electrode pads 14; a secondary interconnections 18 electrically connected to the electrode pads 14; an insulating film 20 formed in a place in between the secondary interconnections on the passivation film 16; and a resistor 26 formed 18 in a predetermined place in between the secondary interconnections 18 on the insulating film 20.
摘要翻译：为了提供一种薄膜电阻器及其制造方法，其能够通过降低电阻器和衬底之间的寄生电容来抑制变容二极管的Q值的降低，所以薄膜电阻器包括半导体衬底10，其包括集成电路12具有多个电极焊盘14，多个电极焊盘14在多个堆叠互连的最上部彼此间隔一定距离，并且集成电路12具有形成在多个电极焊盘14之间的钝化膜16; 电连接到电极焊盘14的次级互连18; 绝缘膜20形成在钝化膜16上的次互连之间的位置; 以及在绝缘膜20上的次级互连18之间的预定位置形成18的电阻器26。

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