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    • 1. 发明申请
    • SELECTIVE SHORTING FOR CLOCK GRID
    • 时钟选择性短片
    • US20120054530A1
    • 2012-03-01
    • US13036287
    • 2011-02-28
    • Kim SCHUTTENBERGFranco RICCI
    • Kim SCHUTTENBERGFranco RICCI
    • G06F1/04
    • G06F1/10
    • Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.
    • 描述了与选择性短路相关联的系统,方法和其他实施例。 根据一个实施例,一种装置包括连接在时钟分支之间的选择性短路装置。 选择性短路装置被配置为选择性地将时钟分支电连接到彼此并且选择性地将时钟分支彼此电断开。 该装置还包括选择性短路控制机构,其控制选通短路装置在时钟信号的控制部分期间电连接时钟分支。 选择性短路控制机构被配置为在没有控制部分的情况下电时断开时钟分支。
    • 2. 发明授权
    • Systems and methods for reducing interrupt latency
    • 减少中断延迟的系统和方法
    • US09116742B1
    • 2015-08-25
    • US13550755
    • 2012-07-17
    • Kim SchuttenbergSujat JamilR. Frank O'Bleness
    • Kim SchuttenbergSujat JamilR. Frank O'Bleness
    • G06F15/00G06F9/48
    • G06F9/4812G06F9/3842G06F9/3861
    • Systems, methods, and other embodiments associated with reducing interrupt latency are described. According to one embodiment, an apparatus includes a buffer storing instructions awaiting execution by an execution device. The apparatus also includes an interrupt logic that, in response to receiving an interrupt, classifies instructions as either safe or unsafe. An unsafe instruction will cause the instructions to execute in a manner inconsistent with an instruction set architecture. The interrupt logic also establishes an interrupt boundary between safe and unsafe instructions, and causes the interrupt to be processed at the interrupt boundary such that the interrupt is processed before processing of the unsafe instructions.
    • 描述了与减少中断延迟相关联的系统,方法和其他实施例。 根据一个实施例,一种装置包括存储执行装置等待执行的指令的缓冲器。 该装置还包括中断逻辑,响应于接收中断,将指令分类为安全或不安全。 不安全的指令将导致指令以不符合指令集架构的方式执行。 中断逻辑还建立安全和不安全指令之间的中断边界,并使中断在中断边界处理,以便在处理不安全指令之前对中断进行处理。
    • 3. 发明授权
    • Selective shorting for clock grid during a controlling portion of a clock signal
    • 在时钟信号的控制部分期间用于时钟网格的选择性短路
    • US08607090B2
    • 2013-12-10
    • US13036287
    • 2011-02-28
    • Kim SchuttenbergFranco Ricci
    • Kim SchuttenbergFranco Ricci
    • G06F1/04
    • G06F1/10
    • Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.
    • 描述了与选择性短路相关联的系统,方法和其他实施例。 根据一个实施例,一种装置包括连接在时钟分支之间的选择性短路装置。 选择性短路装置被配置为选择性地将时钟分支电连接到彼此并且选择性地将时钟分支彼此电断开。 该装置还包括选择性短路控制机构,其控制选通短路装置在时钟信号的控制部分期间电连接时钟分支。 选择性短路控制机构被配置为在没有控制部分的情况下电时断开时钟分支。