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1. 发明授权

US09026769B1 Detecting and reissuing of loop instructions in reorder structure 有权
标题翻译：在重新排序结构中检测和重新发行循环指令
公开(公告)号：US09026769B1
公开(公告)日：2015-05-05
申请号：US13357567
申请日：2012-01-24
申请人： Sujat Jamil , R. Frank O'Bleness , Joseph Delgross , Tom Hameenanttila
发明人： Sujat Jamil , R. Frank O'Bleness , Joseph Delgross , Tom Hameenanttila
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3855 , G06F9/325 , G06F9/381 , G06F9/3836
摘要： A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.
摘要翻译：用于处理循环指令的处理器可以包括指令重排序结构和循环处理控制器。指令重排结构被配置为根据程序顺序存储解码指令，并发出解码指令以执行程序顺序。循环处理控制器被配置为检测存储在指令重排序结构中的解码指令中的循环，并使指令重排序结构重新发出构成循环的解码指令以便重新执行。

2. 发明授权

US08943273B1 Method and apparatus for improving cache efficiency 有权
标题翻译：提高缓存效率的方法和装置
公开(公告)号：US08943273B1
公开(公告)日：2015-01-27
申请号：US12541277
申请日：2009-08-14
申请人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
发明人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
IPC分类号： G06F9/38
CPC分类号： G06F12/0875 , G06F9/30043 , G06F9/3826 , G06F9/3842 , G06F9/3859 , G06F12/0804 , G06F2212/452
摘要： Aspects of the disclosure provide methods for cache efficiency. A method for cache efficiency can include storing data in a buffer entry in association with a cache array in response to a first store instruction that hits the cache array before the first store instruction is committed. Further, when a dependent load instruction is subsequent to the first store instruction, the method can include providing the data from the buffer entry in response to the first dependent load instruction. When a second store instruction overlaps an address of the first store instruction, the method can include coalescing data of the second store instruction in the buffer entry before the second store instruction is committed. When the second store instruction is followed by a second dependent load instruction, the method can include providing the coalesced data from the buffer entry in response to the second dependent load instruction.
摘要翻译：本公开的方面提供了缓存效率的方法。一种用于高速缓存效率的方法可以包括：响应于第一个存储指令在第一个存储指令被提交之前触发高速缓冲存储器阵列，将数据与高速缓冲存储器阵列相关联地存储在缓冲器条目中。此外，当依赖加载指令在第一存储指令之后时，该方法可以包括响应于第一依赖加载指令从缓冲器条目提供数据。当第二存储指令与第一存储指令的地址重叠时，该方法可以包括在提交第二存储指令之前将缓冲器条目中的第二存储指令的数据合并。当第二存储指令后跟第二相关加载指令时，该方法可以包括响应于第二依赖加载指令从缓冲器条目提供合并的数据。

3. 发明授权

US07966477B1 Power optimized replay of blocked operations in a pipilined architecture 有权
标题翻译：在管道架构中的电源优化重播被阻止的操作
公开(公告)号：US07966477B1
公开(公告)日：2011-06-21
申请号：US12782184
申请日：2010-05-18
申请人： Sujat Jamil , Hang Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
发明人： Sujat Jamil , Hang Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
IPC分类号： G06F9/00
CPC分类号： G06F9/3836
摘要： A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.
摘要翻译：一种电源优化重播的方法和装置。在一个实施例中，该方法包括发出从队列中选择的指令。一旦发出，如果指令的完成被检测到的阻塞条件阻挡，则指令可以在再循环队列内排队。一旦排入队列，一旦满足再循环队列内的指令的阻塞状态，包含在再循环队列内的指令就可以重新发出。因此，如本文所述的功率优化重放方案优化功率，同时保留通过有选择地重放阻塞指令而提供的优点，以提高功率效率。

4. 发明授权

US07428607B2 Apparatus and method for arbitrating heterogeneous agents in on-chip busses 有权
标题翻译：用于在片上总线中仲裁异构代理的装置和方法
公开(公告)号：US07428607B2
公开(公告)日：2008-09-23
申请号：US11501572
申请日：2006-08-08
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
IPC分类号： G06F13/36 , G06N7/06
CPC分类号： G06F13/4031 , G06F13/362
摘要： A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.
摘要翻译：一种用于在片上总线上支持异构代理的方法和装置。在一个实施例中，该方法包括在至少第一总线代理和第二总线代理之间检测总线仲裁事件。在一个实施例中，当至少第一总线代理和第二总线代理在单个时钟周期中断言其各自的总线请求信号时，检测总线仲裁事件。一旦检测到总线仲裁事件，当第一总线代理和第二总线代理具有不同的授权 - 有效延迟时，总线所有权可以被授予第一总线代理和第二总线代理两者。在该实施例中，异构总线代理可以在总线上共存而不需要在建立总线所有权之后浪费或未使用的总线周期。描述和要求保护其他实施例。

5. 发明授权

US07406553B2 System and apparatus for early fixed latency subtractive decoding 有权
标题翻译：用于早期固定延迟减法解码的系统和装置
公开(公告)号：US07406553B2
公开(公告)日：2008-07-29
申请号：US11734401
申请日：2007-04-12
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
IPC分类号： G06F13/42
CPC分类号： G06F13/4217
摘要： Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.
摘要翻译：公开了早期固定延迟减法解码的系统和方法。减法解码装置在与正解码的时间段相同的固定时间段内推测性地确认总线事务。因此，可以在每个新的时间段内完成新的公交交易的流水线。如果在固定时间段内没有发生确认，则可以重试总线事务。

6. 发明授权

US07290093B2 Cache memory to support a processor's power mode of operation 有权
标题翻译：缓存内存支持处理器的电源运行模式
公开(公告)号：US07290093B2
公开(公告)日：2007-10-30
申请号：US10338207
申请日：2003-01-07
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/126 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A system, method, and apparatus for a cache memory to support a low power mode of operation.
摘要翻译：一种用于缓存存储器以支持低功率操作模式的系统，方法和装置。

7. 再颁专利

USRE38045E1 Data compensation/resynchronization circuit for phase lock loops 有权
标题翻译：用于锁相环的数据补偿/再同步电路
公开(公告)号：USRE38045E1
公开(公告)日：2003-03-25
申请号：US09612540
申请日：2000-07-07
申请人： Aldo Giovanni Cometti , R. Frank O'Bleness
发明人： Aldo Giovanni Cometti , R. Frank O'Bleness
IPC分类号： H03L706
CPC分类号： H03L7/18 , G06F1/10
摘要： A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.
摘要翻译：公开了一种补偿由锁相环应用中的时钟产生逻辑和分布式时钟驱动引起的延迟的电路。该电路是一个锁相环（PLL），它包含时钟同步电路，该时钟同步电路用于使由分频器产生的信号的过渡沿与电路的时钟输出驱动器产生的分布式时钟信号同步。除非时钟同步电路被禁止，否则发生同步。

8. 发明授权

US08533401B2 Implementing direct access caches in coherent multiprocessors 有权
标题翻译：在一致的多处理器中实现直接访问缓存
公开(公告)号：US08533401B2
公开(公告)日：2013-09-10
申请号：US10331688
申请日：2002-12-30
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.
摘要翻译：诸如总线代理的非处理器代理可以直接访问处理器高速缓存。一致性协议确保高速缓存一致性得到维护。

9. 发明授权

US08458404B1 Programmable cache access protocol to optimize power consumption and performance 有权
标题翻译：可编程缓存访问协议，以优化功耗和性能
公开(公告)号：US08458404B1
公开(公告)日：2013-06-04
申请号：US12540788
申请日：2009-08-13
申请人： Joseph Delgross , Sujat Jamil , R. Frank O'Bleness , Tom Hameenanttila , David E. Miner
发明人： Joseph Delgross , Sujat Jamil , R. Frank O'Bleness , Tom Hameenanttila , David E. Miner
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/502 , G06F2212/601 , Y02D10/13
摘要： A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.
摘要翻译：可编程高速缓存和缓存访问协议，可根据高速缓存的受监控性能，针对功耗或性能进行动态优化。监视单元监视高速缓存未命中，加载使用罚分和/或其他性能参数，并将所监视的值与一组或多个预定阈值进行比较。基于比较结果，高速缓存控制器将可编程高速缓存器配置为以并行模式操作，以牺牲更大功耗或串行模式为代价来增加高速缓存性能，从而以不必要的性能为代价来节省功耗。还描述了一种使用库存访问策略来支持对齐和未对齐指令取出的存储缓存，并且还描述了包括预取能力的高速缓存访问控制器。

10. 发明授权

US08296525B1 Method and apparatus for data-less bus query 有权
标题翻译：无数据总线查询的方法和装置
公开(公告)号：US08296525B1
公开(公告)日：2012-10-23
申请号：US12537857
申请日：2009-08-07
申请人： Frank O'Bleness , Sujat Jamil , David E. Miner , Tom Hameenanttila , Jeffrey Kehl , Richard Bryant , Kim Schuttenberg
发明人： Frank O'Bleness , Sujat Jamil , David E. Miner , Tom Hameenanttila , Jeffrey Kehl , Richard Bryant , Kim Schuttenberg
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.
摘要翻译：在具有使用一个或多个跟踪队列的多个响应者的系统中跟踪多个非识别标记请求的系统和方法。在一些实施例中，系统和方法可以在覆盖多个高速缓存的窥探过滤器中实现。在一些实施例中，可以使用无数据总线查询来更新所请求行的状态。

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