专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07953987B2 Protection of secure electronic modules against attacks 失效
标题翻译：保护安全的电子模块免受攻击
公开(公告)号：US07953987B2
公开(公告)日：2011-05-31
申请号：US11682349
申请日：2007-03-06
申请人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
发明人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
IPC分类号： G06F12/14
CPC分类号： G06F21/86 , G06F2221/2143
摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.
摘要翻译：公开了一种用于防止由安全电子模块中的优选状态/老化引起的秘密数据的意外保留的方法和装置。在交替的时钟周期内顺序存储数据及其反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销擦除较大的存储区域。

2. 发明申请

US20140185795A1 FUSE ATTESTATION TO SECURE THE PROVISIONING OF SECRET KEYS DURING INTEGRATED CIRCUIT MANUFACTURING 有权
标题翻译：保险丝安全确保集成电路制造过程中秘密钥匙的提供
公开(公告)号：US20140185795A1
公开(公告)日：2014-07-03
申请号：US13728375
申请日：2012-12-27
申请人： Kevin C. Gotze , Jiangtao Li , Gregory M. Iovino
发明人： Kevin C. Gotze , Jiangtao Li , Gregory M. Iovino
IPC分类号： H04L9/08
CPC分类号： G06F21/73 , G06F21/44 , G09C1/00 , H04L9/0861 , H04L9/0866 , H04L9/3278
摘要： Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses.
摘要翻译：公开了用于在集成电路制造期间确保秘密密钥供应的熔丝证明的发明的实施例。在一个实施例中，一种装置包括存储位置，物理上不可克隆功能（PUF）电路，PUF密钥发生器，加密单元和多个保险丝。存储位置是存储配置熔丝值。 PUF电路提供PUF值。 PUF密钥生成器基于PUF值生成PUF密钥。加密单元使用PUF密钥加密配置熔丝值。 PUF键和配置保险丝值将提供给密钥服务器。密钥服务器是确定配置熔丝值表示该设备是生产部件，并且作为响应，提供要存储在多个保险丝中的熔丝钥匙。

3. 发明申请

US20140123281A1 DETECTION OF RETURN ORIENTED PROGRAMMING ATTACKS 有权
标题翻译：返回面向编程攻击的检测
公开(公告)号：US20140123281A1
公开(公告)日：2014-05-01
申请号：US13664532
申请日：2012-10-31
申请人： Stephen A. Fischer , Kevin C. Gotze , Yuriy Bulygin , Kirk D. Brannock
发明人： Stephen A. Fischer , Kevin C. Gotze , Yuriy Bulygin , Kirk D. Brannock
IPC分类号： G06F21/00
CPC分类号： G06F21/552 , G06F9/30145 , G06F21/566 , G06F2221/034
摘要： In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
摘要翻译：在一个实施例中，处理器包括至少一个执行单元和返回定向编程（ROP）检测逻辑。 ROP检测逻辑可以基于多个控制传送事件来确定ROP度量。 ROP检测逻辑还可以确定ROP度量是否超过阈值。 ROP检测逻辑还可以响应于ROP度量超过阈值的确定，提供ROP攻击通知。

4. 发明申请

US20090210760A1 Analog Testing of Ring Oscillators Using Built-In Self Test Apparatus 失效
标题翻译：使用内置自检装置的环形振荡器的模拟测试
公开(公告)号：US20090210760A1
公开(公告)日：2009-08-20
申请号：US12032649
申请日：2008-02-16
申请人： Joseph E. Eckelman , Kevin C. Gotze , James A. Kyle , Jennifer Yuk Sim Yan
发明人： Joseph E. Eckelman , Kevin C. Gotze , James A. Kyle , Jennifer Yuk Sim Yan
IPC分类号： G01R31/3181
CPC分类号： G01R31/318502 , G01R31/2824 , G01R31/2884 , G01R31/31727
摘要： System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed. Test interrogations are distributed on-chip through an LSSD shift register chain to individually evaluate each of a plurality of the oscillators.
摘要翻译：系统可访问的频率测量电路和程序允许对振荡器进行片上测试，并通过LSSD扫描路径提供可观察到的芯片外的测试结果。这允许在标准ASIC测试流程中快速地组合环形振荡器，而不需要片上模拟测试设备（测试设备已经在设备上有效地创建并且可以被数字地配置，操作和读取）。频率测量逻辑，可以1）功能操作来测量环形振荡器的频率; 2）参与传统的逻辑测试，如LSSD和LBIST，以验证电路是否正确制造，并且可能运行，以及3）以特殊的环形振荡器测试模式工作，这允许逻辑在测试仪上工作，非常类似于它在功能上的方式。在这种模式下，频率测量逻辑可以被扫描到一个特定的状态，通过脉冲数字I / O开始，测量的模拟值可以在测试完成后的某个时间被扫描出来。测试询问通过LSSD移位寄存器链在芯片上分布，以分别评估多个振荡器中的每一个。

5. 发明授权

US07768005B2 Physically highly secure multi-chip assembly 有权
标题翻译：物理上高度安全的多芯片组装
公开(公告)号：US07768005B2
公开(公告)日：2010-08-03
申请号：US12129040
申请日：2008-05-29
申请人： Vincenzo Condorelli , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
发明人： Vincenzo Condorelli , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L23/5383 , H01L2224/16 , H01L2224/16225 , H01L2224/73204 , H01L2924/01078 , H01L2924/10253 , H01L2924/15311 , H01L2924/19103 , H01L2924/19107 , Y10T29/53039 , Y10T29/53052 , Y10T29/53178 , H01L2924/00
摘要： A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
摘要翻译：提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。电导体围绕导电路径。监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

6. 发明申请

US20080231311A1 PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY 有权
标题翻译：物理安全的多芯片组件
公开(公告)号：US20080231311A1
公开(公告)日：2008-09-25
申请号：US12129040
申请日：2008-05-29
申请人： VINCENZO CONDORELLI , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
发明人： VINCENZO CONDORELLI , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
IPC分类号： G01R31/26
CPC分类号： H01L23/576 , H01L23/5383 , H01L2224/16 , H01L2224/16225 , H01L2224/73204 , H01L2924/01078 , H01L2924/10253 , H01L2924/15311 , H01L2924/19103 , H01L2924/19107 , Y10T29/53039 , Y10T29/53052 , Y10T29/53178 , H01L2924/00
摘要： A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
摘要翻译：提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。电导体围绕导电路径。监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

7. 发明授权

US07402442B2 Physically highly secure multi-chip assembly 有权
标题翻译：物理上高度安全的多芯片组装
公开(公告)号：US07402442B2
公开(公告)日：2008-07-22
申请号：US11314272
申请日：2005-12-21
申请人： Vincenzo Condorelli , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
发明人： Vincenzo Condorelli , Claudius Feger , Kevin C. Gotze , Nihad Hadzic , John U. Knickerbocker , Edmund J. Sprogis
IPC分类号： H01L23/58 , H01L21/00 , B23Q15/00
CPC分类号： H01L23/576 , H01L23/5383 , H01L2224/16 , H01L2224/16225 , H01L2224/73204 , H01L2924/01078 , H01L2924/10253 , H01L2924/15311 , H01L2924/19103 , H01L2924/19107 , Y10T29/53039 , Y10T29/53052 , Y10T29/53178 , H01L2924/00
摘要： A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
摘要翻译：提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。电导体围绕导电路径。监视电路检测一个或多个电导体的连续性断裂，并且优选地使组件不可操作。优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

8. 发明申请

US20140093074A1 SECURE PROVISIONING OF SECRET KEYS DURING INTEGRATED CIRCUIT MANUFACTURING 有权
标题翻译：在集成电路制造过程中安全提供秘密钥匙
公开(公告)号：US20140093074A1
公开(公告)日：2014-04-03
申请号：US13631512
申请日：2012-09-28
申请人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li
发明人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li
IPC分类号： H04L9/00
CPC分类号： H04L9/0866 , H04L9/3278
摘要： A method, of an aspect, includes challenging a set of Physically Unclonable Function (PUF) cells, of an integrated circuit device, and receiving a set of PUF bits from the PUF cells in response. A PUF key is generated based on the set of PUF bits. An encryption of the PUF key with an embedded key is output from the integrated circuit device. The integrated circuit device receives an encryption of a fuse key with the PUF key. Fuses of the integrated circuit device are programmed with at least one of the fuse key and the received encryption of the fuse key with the PUF key. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一方面的方法包括挑战集成电路设备的一组物理不可克隆功能（PUF）单元，以及响应于从PUF单元接收一组PUF位。基于PUF位的集合生成PUF密钥。从集成电路设备输出使用嵌入式密钥对PUF密钥的加密。集成电路装置利用PUF键接收熔丝钥匙的加密。集成电路装置的保险丝用熔丝钥匙和熔丝钥匙的接收加密中的至少一个与PUF密钥进行编程。还公开了其它方法，装置和系统。

9. 发明申请

US20140091832A1 INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：具有可接受和不可接受的物理不可靠功能的集成电路
公开(公告)号：US20140091832A1
公开(公告)日：2014-04-03
申请号：US13631634
申请日：2012-09-28
申请人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
发明人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.
摘要翻译：一方面的集成电路基板包括多个暴露的电触点。集成电路基板还包括不可接近的物理不可克隆功能（PUF）单元组，以生成不能通过暴露的电触点访问的不可访问的PUF位集合。集成电路基板还包括可访问的PUF单元组，以产生可通过暴露的电触点访问的可访问的PUF位组。还公开了其他装置，方法和系统。

10. 发明授权

US07765445B2 Analog testing of ring oscillators using built-in self test apparatus 失效
标题翻译：使用内置自检装置对环形振荡器进行模拟测试
公开(公告)号：US07765445B2
公开(公告)日：2010-07-27
申请号：US12032649
申请日：2008-02-16
申请人： Joseph E. Eckelman , Kevin C. Gotze , James A. Kyle , Jennifer Yuk Sim Yan
发明人： Joseph E. Eckelman , Kevin C. Gotze , James A. Kyle , Jennifer Yuk Sim Yan
IPC分类号： G01R31/28
CPC分类号： G01R31/318502 , G01R31/2824 , G01R31/2884 , G01R31/31727
摘要： System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed. Test interrogations are distributed on-chip through an LSSD shift register chain to individually evaluate each of a plurality of the oscillators.
摘要翻译：系统可访问的频率测量电路和程序允许对振荡器进行片上测试，并通过LSSD扫描路径提供可观察到的芯片外的测试结果。这允许在标准ASIC测试流程中快速地组合环形振荡器，而不需要片上模拟测试设备（测试设备已经在设备上有效地创建并且可以被数字地配置，操作和读取）。频率测量逻辑，可以1）功能操作来测量环形振荡器的频率; 2）参与传统的逻辑测试，如LSSD和LBIST，以验证电路是否正确制造，并且可能运行，以及3）以特殊的环形振荡器测试模式工作，允许逻辑在测试仪上工作，非常类似于它在功能上的方式。在这种模式下，频率测量逻辑可以被扫描到一个特定的状态，通过脉冲数字I / O开始，测量的模拟值可以在测试完成后的某个时间被扫描出来。测试询问通过LSSD移位寄存器链在芯片上分布，以分别评估多个振荡器中的每一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式