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1. 发明授权

US09673300B2 Semiconductor devices including a gate core and a fin active core and methods of fabricating the same 有权
公开(公告)号：US09673300B2
公开(公告)日：2017-06-06
申请号：US14820860
申请日：2015-08-07
申请人： Seungseok Ha , Keunhee Bai , Kyounghwan Yeo , Eunsil Park , Heonjong Shin
发明人： Seungseok Ha , Keunhee Bai , Kyounghwan Yeo , Eunsil Park , Heonjong Shin
IPC分类号： H01L21/762 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/76229 , H01L29/66545
摘要： Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.

2. 发明申请

US20060154460A1 Self-aligned contact method 审中-公开
标题翻译：自对准接触方式
公开(公告)号：US20060154460A1
公开(公告)日：2006-07-13
申请号：US11293126
申请日：2005-12-05
申请人： Serah Yun , Changki Hong , Jaedong Lee , Juseon Goo , Youngok Kim , Jeongheon Park , Joonsang Park , Keunhee Bai , Myoungho Jung
发明人： Serah Yun , Changki Hong , Jaedong Lee , Juseon Goo , Youngok Kim , Jeongheon Park , Joonsang Park , Keunhee Bai , Myoungho Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897
摘要： In one aspect, a self-aligned contact method is provided in which a substrate having a plurality of structures are spaced apart over a surface of the substrate, and a sacrificial film is deposited over and between the plurality of structures, where a material of the sacrificial film has a given withstand temperature. The sacrificial film is patterned to expose a portion of the substrate adjacent the plurality of structures. An insulating layer is deposited over the sacrificial film and the exposed portion of the substrate, where the depositing of the insulating layer includes a heat treatment at a temperature which is less than the withstand temperature of the sacrificial film material. The insulating layer is planarized to expose the sacrificial film, and the sacrificial film is removed to expose respective areas between the plurality of structures. The respective areas between the plurality of structures are filled with a conductive material.
摘要翻译：在一个方面，提供一种自对准接触方法，其中具有多个结构的衬底在衬底的表面上间隔开，并且牺牲膜沉积在多个结构之间并且在多个结构之间，其中，牺牲膜具有给定的耐受温度。牺牲膜被图案化以暴露与多个结构相邻的衬底的一部分。绝缘层沉积在牺牲膜和衬底的暴露部分上，其中绝缘层的沉积包括在小于牺牲膜材料的耐受温度的温度下的热处理。平面化绝缘层以暴露牺牲膜，并且去除牺牲膜以暴露多个结构之间的相应区域。多个结构之间的各个区域填充有导电材料。

3. 发明申请

US20160111524A1 SEMICONDUCTOR DEVICES INCLUDING A GATE CORE AND A FIN ACTIVE CORE AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包括门芯和精细活动核心的半导体器件及其制造方法
公开(公告)号：US20160111524A1
公开(公告)日：2016-04-21
申请号：US14820860
申请日：2015-08-07
申请人： Seungseok HA , Keunhee BAI , Kyounghwan YEO , Eunsil PARK , Heonjong SHIN
发明人： Seungseok HA , Keunhee BAI , Kyounghwan YEO , Eunsil PARK , Heonjong SHIN
IPC分类号： H01L29/66 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/76229 , H01L29/66545
摘要： Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.
摘要翻译：提供半导体器件及其制造方法。所述方法可以包括形成限定翅片有源区域的隔离区域，在隔离区域上形成牺牲场栅极图案，并在翅片有源区域上形成牺牲鳍栅极图案。该方法还可以包括形成场栅切割区，其包括露出隔离区的表面的第一凹部和鳍片主动切割区，其包括暴露翅片有源区的表面的第二凹部，在第二凹部中形成翅片活动凹部的翅片活动切割区域，并且通过在场浇口切割区域的第一凹部和翅片活动凹部中分别形成绝缘材料，分别形成场门芯和翅片活动芯。

4. 发明授权

US09978746B2 Semiconductor devices and methods of manufacturing the same 有权
公开(公告)号：US09978746B2
公开(公告)日：2018-05-22
申请号：US15059423
申请日：2016-03-03
申请人： Kyoung Hwan Yeo , KeunHee Bai , Seungseok Ha , Eunsil Park , Sunhom Steve Paak , Heonjong Shin , Dongho Cha
发明人： Kyoung Hwan Yeo , KeunHee Bai , Seungseok Ha , Eunsil Park , Sunhom Steve Paak , Heonjong Shin , Dongho Cha
IPC分类号： H01L27/088 , H01L29/06 , H01L27/11 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823481 , H01L27/0886 , H01L27/1104 , H01L29/0653 , H01L29/7848
摘要： Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.

5. 发明申请

US20160307890A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160307890A1
公开(公告)日：2016-10-20
申请号：US15059423
申请日：2016-03-03
申请人： Kyoung Hwan Yeo , KeunHee Bai , Seungseok Ha , Eunsil Park , Sunhom Steve Paak , Heonjong Shin , Dongho Cha
发明人： Kyoung Hwan Yeo , KeunHee Bai , Seungseok Ha , Eunsil Park , Sunhom Steve Paak , Heonjong Shin , Dongho Cha
IPC分类号： H01L27/088 , H01L29/06 , H01L27/105
CPC分类号： H01L27/088 , H01L21/823481 , H01L27/0886 , H01L27/1104 , H01L29/0653 , H01L29/7848
摘要： Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.
摘要翻译：提供了具有场效应晶体管的半导体器件。半导体器件可以包括包括有源图案的衬底，与有源图案交叉的分离结构，并将活性图案分成第一和第二区域。分离结构可以包括填充第一和第二区域之间的凹部区域的第一绝缘图案。第一绝缘图案可以具有凹的顶表面。

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