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1. 发明申请

US20090185649A1 Decision Directed Flicker Noise Cancellation 有权
标题翻译：决定定向闪烁噪声消除
公开(公告)号：US20090185649A1
公开(公告)日：2009-07-23
申请号：US12356037
申请日：2009-01-19
申请人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
发明人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
IPC分类号： H04B1/10
CPC分类号： H04L27/0008 , H04B1/30 , H04B1/7101
摘要： A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.
摘要翻译：根据本发明的实施例的用于减少调制输入信号中的闪烁噪声的决策指示闪烁噪声消除器包括判定电路，转换电路，第一和第二加法器和滤波器。判定电路基于输入信号提供信号判定。转换电路根据信号决定提供所选择的信号值。第一加法器基于输入信号从信号中减去所选择的信号值，以提供闪烁噪声估计。滤波器接收并滤除闪烁噪声估计，第二加法器从输入信号中减去经滤波的闪烁噪声估计，并提供经校正的输入信号。在反馈配置中，第二加法器位于信号处理路径中的判定电路之前的反馈位置。在前馈配置中，第二加法器位于决定电路之后的前馈位置。

2. 发明授权

US07058144B2 Intelligent control system and method for compensation application in a wireless communications system 有权
公开(公告)号：US07058144B2
公开(公告)日：2006-06-06
申请号：US10121762
申请日：2002-04-12
申请人： Keith R. Baldwin
发明人： Keith R. Baldwin
IPC分类号： H04B1/10 , H03H7/30
CPC分类号： H04L1/20 , H04L25/0212
摘要： A wireless receiver including a baseband processor that includes a compensation system that selectively includes an equalizer and a CMF that process received digital samples from a wireless medium, and a CIR estimator that calculates filter weights based on the samples. A memory stores default filter weights and select logic selects between calculated filter weights of the CIR estimator and the default filter weights from the memory. An SNR estimator receives the samples and provides an SNR metric and a multipath estimator receives the calculated filter weights and provides a multipath metric. The decision logic determines an operating point of the receiver using the SNR and multipath metrics, makes a decision based on the determined operating point according to a predetermined packet error rate (PER) performance mapping, and controls the select logic to select between the default and calculated filter weights and selectively enables the equalizer.

3. 发明授权

US06735422B1 Calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture 有权
标题翻译：用于零中频架构配置的无线通信设备的校准直流补偿系统
公开(公告)号：US06735422B1
公开(公告)日：2004-05-11
申请号：US09677975
申请日：2000-10-02
申请人： Keith R. Baldwin , Patrick J. Landy , Mark A. Webster , R. Douglas Schultz , John S. Prentice
发明人： Keith R. Baldwin , Patrick J. Landy , Mark A. Webster , R. Douglas Schultz , John S. Prentice
IPC分类号： H04B106
CPC分类号： H04B1/30 , H03D3/008 , H03D3/009 , H03L7/0812 , H03L7/085 , H04L27/0014 , H04L2027/0016
摘要： A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency (ZIF) architecture. The device includes a ZIF transceiver and a baseband processor, which further includes a calibrator that periodically performs a calibration procedure. The baseband processor includes gain control logic, DC control logic, a gain converter and the calibrator. The gain converter converts gain between the gain control logic and the DC control logic. The calibrator programs the gain converter with values determined during the calibration procedure. The gain converter may be a lookup table that stores gain conversion values based on measured gain of a baseband gain amplifier of the ZIF transceiver. The gain control logic may further include a gain adjust limiter that limits change of a gain adjust signal during operation based on a maximum limit or on one or more gain change limits. A second lookup table stores a plurality of DC adjust values, which are added during operation to further reduce DC offset. The calibration procedure includes sampling an output signal for each gain step of the baseband amplifier at two predetermined range values and corresponding DC offsets using successive approximation. The data is used to calculate gain, DC offset and DC differential values, which are used to determine the conversion values programmed into the lookup tables or the gain adjust limiter.
摘要翻译：一种用于以零中频（ZIF）架构配置的无线通信设备的校准DC补偿系统。该设备包括ZIF收发器和基带处理器，其还包括定期执行校准过程的校准器。基带处理器包括增益控制逻辑，直流控制逻辑，增益转换器和校准器。增益转换器在增益控制逻辑和直流控制逻辑之间转换增益。校准器使用在校准过程中确定的值来对增益转换器进行编程。增益转换器可以是基于ZIF收发器的基带增益放大器的测量增益来存储增益转换值的查找表。增益控制逻辑还可以包括增益调节限制器，其限制在运行期间增益调整信号的变化，其基于最大限制或一个或多个增益变化限制。第二查找表存储多个DC调整值，其在操作期间被添加以进一步减少DC偏移。校准过程包括使用逐次近似在两个预定范围值和相应的DC偏移下对基带放大器的每个增益步长的输出信号进行采样。该数据用于计算增益，直流偏移和直流差分值，用于确定编入查找表或增益调节限制器的转换值。

4. 发明授权

US07489747B2 Decision directed flicker noise cancellation 有权
标题翻译：决定指示闪烁噪声消除
公开(公告)号：US07489747B2
公开(公告)日：2009-02-10
申请号：US10778854
申请日：2004-02-13
申请人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
发明人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
IPC分类号： H03D1/04
CPC分类号： H04L27/0008 , H04B1/30 , H04B1/7101
摘要： A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.
摘要翻译：根据本发明的实施例的用于减少调制输入信号中的闪烁噪声的决策指示闪烁噪声消除器包括判定电路，转换电路，第一和第二加法器和滤波器。判定电路基于输入信号提供信号判定。转换电路根据信号决定提供所选择的信号值。第一加法器基于输入信号从信号中减去所选择的信号值，以提供闪烁噪声估计。滤波器接收并滤除闪烁噪声估计，第二加法器从输入信号中减去经滤波的闪烁噪声估计，并提供经校正的输入信号。在反馈配置中，第二加法器位于信号处理路径中的判定电路之前的反馈位置。在前馈配置中，第二加法器位于决定电路之后的前馈位置。

5. 发明授权

US07068987B2 Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture 有权
公开(公告)号：US07068987B2
公开(公告)日：2006-06-27
申请号：US09918409
申请日：2001-07-30
申请人： Keith R. Baldwin , Mark A. Webster
发明人： Keith R. Baldwin , Mark A. Webster
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03D3/008 , H03L7/0812 , H03L7/085 , H04B1/30 , H04L25/061
摘要： A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture including a DC loop and a gain loop. The method includes processing energy in a wireless medium to generate a corresponding receive signal, monitoring the receive signal via a predetermined measurement window, detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop in an attempt to search a stable DC value for the receive signal while the gain loop is held constant. A first case is DC saturation, where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet. A third case is preparation for receiving an expected acknowledgement packet after transmitting a packet, where again a prior stored gain setting is applied to the gain loop and DC is searched.

6. 发明授权

US06724834B2 Threshold detector for detecting synchronization signals at correlator output during packet acquisition 有权
标题翻译：阈值检测器，用于在分组获取期间检测相关器输出端的同步信号
公开(公告)号：US06724834B2
公开(公告)日：2004-04-20
申请号：US10081045
申请日：2002-02-22
申请人： Albert L. Garrett , Keith R. Baldwin
发明人： Albert L. Garrett , Keith R. Baldwin
IPC分类号： H04L2510
CPC分类号： H04L27/2662 , H04L7/042 , H04L27/2675 , H04L27/2695
摘要： A threshold detector for detecting synchronization signals at correlator output during packet acquisition. An RF receiver converts RF signals into baseband signals. A matched filter correlator correlates samples of the baseband signals with predetermined synchronization signals, such as long sync symbols, and provides corresponding correlation samples. A long-term integrator integrates a first predetermined number of the correlation samples to provide a long term moving average and a short term integrator integrates a second predetermined number of the correlation samples to provide a short term moving average signal. The short term moving average signal is based on channel delay spread and the long term moving average tracks channel noise. A multiplier multiplies the long term moving average signal by a scale factor to generate a dynamic threshold. A detector detects a crossover between the short term moving average and the dynamic threshold to estimate timing of received synchronization signals.
摘要翻译：一种用于在分组获取期间在相关器输出端检测同步信号的阈值检测器。 RF接收机将RF信号转换为基带信号。匹配滤波器相关器将基带信号的采样与诸如长同步符号的预定同步信号相关联，并提供相应的相关采样。长期积分器将第一预定数量的相关采样积分以提供长期移动平均线，并且短期积分器将第二预定数量的相关采样积分以提供短期移动平均信号。短期移动平均信号基于信道延迟扩展，长期移动平均信号跟踪信道噪声。乘法器将长期移动平均信号乘以比例因子以产生动态阈值。检测器检测短期移动平均和动态阈值之间的交叉以估计接收到的同步信号的定时。

7. 发明授权

US06560448B1 DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture 有权
标题翻译：用于在零中频架构中配置的无线通信设备的DC补偿系统
公开(公告)号：US06560448B1
公开(公告)日：2003-05-06
申请号：US09678901
申请日：2000-10-02
申请人： Keith R. Baldwin , Patrick J. Landy , Mark A. Webster , R. Douglas Schultz , John S. Prentice
发明人： Keith R. Baldwin , Patrick J. Landy , Mark A. Webster , R. Douglas Schultz , John S. Prentice
IPC分类号： H04B106
CPC分类号： H04B1/30 , H03D3/008
摘要： A wireless communication device including a radio frequency (RF) circuit, a ZIF transceiver and a baseband processor. The ZIF transceiver includes an RF mixer circuit that converts the RF signal to a baseband input signal, a summing junction that subtracts a DC offset from the baseband input signal to provide an adjusted baseband input signal, and a baseband amplifier that receives the adjusted baseband input signal and that asserts an amplified input signal based on a gain adjust signal. The baseband processor includes gain control logic, DC control logic and a gain interface. The gain control logic receives the amplified input signal, estimates input signal power and asserts the gain adjust signal in an attempt to keep the input signal power at a target power level. The DC control logic estimates an amount of DC in the amplified input signal and provides the DC offset in an attempt to reduce DC in the amplified input signal. The gain interface converts gain levels between the gain control logic and the DC control logic. The RF signal may include in-phase (I) and quadrature (Q) portions, where the RF mixer circuit splits I and Q baseband input signals from the RF signal. Operation is substantially identical for both I and Q channels. The DC control logic operates to remove or otherwise eliminate DC from the received signal that is provided to decoders in the baseband processor.
摘要翻译：一种包括射频（RF）电路，ZIF收发器和基带处理器的无线通信设备。 ZIF收发器包括将RF信号转换为基带输入信号的RF混频器电路，从基带输入信号减去DC偏移以提供经调整的基带输入信号的加法结以及接收经调整的基带输入的基带放大器信号，并且基于增益调整信号确定放大的输入信号。基带处理器包括增益控制逻辑，直流控制逻辑和增益接口。增益控制逻辑接收放大的输入信号，估计输入信号功率并且确定增益调整信号以试图将输入信号功率保持在目标功率电平。 DC控制逻辑估计放大输入信号中的DC量，并提供DC偏移以试图减小放大的输入信号中的DC。增益接口转换增益控制逻辑和直流控制逻辑之间的增益电平。 RF信号可以包括同相（I）和正交（Q）部分，其中RF混频器电路从RF信号分离I和Q基带输入信号。 I和Q通道的操作基本相同。 DC控制逻辑操作以从提供给基带处理器中的解码器的接收信号中去除或以其他方式消除DC。

8. 发明授权

US5500879A Blind signal separation and equalization of full-duplex amplitude modulated signals on a signal transmission line 失效
标题翻译：信号传输线上全双工幅度调制信号的盲信号分离和均衡
公开(公告)号：US5500879A
公开(公告)日：1996-03-19
申请号：US213886
申请日：1994-03-16
申请人： Mark A. Webster , Keith R. Baldwin , Richard D. Roberts
发明人： Mark A. Webster , Keith R. Baldwin , Richard D. Roberts
IPC分类号： H04B3/23 , H03K7/02
CPC分类号： H04B3/23 , H04L25/0266 , H03H2021/0034
摘要： An apparatus for blind signal separation and equalization of PAM signals on a full duplex transmission line is capable of successfully extracting and recovering the respective signalling components of a full-duplex wireline digital data link without having to disturb the link during its use (e.g. as by interrupting service to sever the link in order to install a line coupling device, such as a modem or attenuator pad to signal monitoring equipment) and without having to generate PN or other training sequences. A full-duplex wireline bridge device comprises a signal characteristic monitoring device that is capable of monitoring the link and providing respective output signals representative of the respective unidirectional signal components being transmitted simultaneously in opposite directions along the link. A directional signal separator, comprised of a voltage probe and a current probe, each of which can be coupled to the link without severing the link or otherwise disrupting ongoing communications, couples the signal characteristic monitoring device to the link. The signal processing device is operative to controllably combine the outputs of the voltage and current probes and provides respective output signals that are representative of the desired unidirectional signal components. The communications link may be either a single wire transmission line or a two wire balanced transmission line. In the latter instance individual probes of pairs of voltage and current probes are coupled to respective portions of the two wire balanced transmission line.
摘要翻译：用于全双工传输线上的PAM信号的盲信号分离和均衡的装置能够成功地提取和恢复全双工有线数字数据链路的各个信令分量，而不必在其使用期间干扰链路（例如，如中断服务以切断链路，以便安装线路耦合设备，例如调制解调器或衰减器垫来信号监测设备），而不必生成PN或其他训练序列。全双工有线电桥装置包括信号特征监测装置，其能够监测链路并提供表示沿着链路沿相反方向同时传输的相应单向信号分量的相应输出信号。定向信号分离器，包括电压探头和电流探头，每个可以耦合到链路而不中断链路或以其他方式中断正在进行的通信，将信号特征监测装置耦合到链路。信号处理装置可操作地组合电压和电流探头的输出，并提供表示期望的单向信号分量的相应的输出信号。通信链路可以是单线传输线路或二线平衡传输线路。在后一种情况下，电压和电流探针对的单个探针耦合到两线平衡传输线的相应部分。

9. 发明授权

US08254504B2 Decision directed flicker noise cancellation 有权
标题翻译：决定指示闪烁噪声消除
公开(公告)号：US08254504B2
公开(公告)日：2012-08-28
申请号：US12356037
申请日：2009-01-19
申请人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
发明人： Mark A. Webster , Alex C. Yeh , Keith R. Baldwin
IPC分类号： H04B1/10 , H04L27/06 , H04L27/00
CPC分类号： H04L27/0008 , H04B1/30 , H04B1/7101
摘要： A decision directed flicker noise canceller for reducing flicker noise in a modulated input signal according to an embodiment of the present invention includes a decision circuit, a conversion circuit, first and second adders and a filter. The decision circuit provides signal decisions based on the input signal. The conversion circuit provides selected signal values based on the signal decisions. The first adder subtracts the selected signal values from signals based on the input signal to provide a flicker noise estimate. The filter receives and filters the flicker noise estimate and the second adder subtracts the filtered flicker noise estimate from the input signal and provides a corrected input signal. In a feedback configuration, the second adder is located in a feedback position before the decision circuit in the signal processing path. In a feed-forward configuration, the second adder is located in a feed-forward position after the decision circuit.
摘要翻译：根据本发明的实施例的用于减少调制输入信号中的闪烁噪声的决策指示闪烁噪声消除器包括判定电路，转换电路，第一和第二加法器和滤波器。判定电路基于输入信号提供信号判定。转换电路根据信号决定提供所选择的信号值。第一加法器基于输入信号从信号中减去所选择的信号值，以提供闪烁噪声估计。滤波器接收并滤除闪烁噪声估计，第二加法器从输入信号中减去经滤波的闪烁噪声估计，并提供经校正的输入信号。在反馈配置中，第二加法器位于信号处理路径中的判定电路之前的反馈位置。在前馈配置中，第二加法器位于决定电路之后的前馈位置。

10. 再颁专利

USRE42799E1 Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture 有权
标题翻译：在零中频架构中配置的无线通信设备的数据包采集和信道跟踪
公开(公告)号：USRE42799E1
公开(公告)日：2011-10-04
申请号：US12147975
申请日：2008-06-27
申请人： Keith R. Baldwin , Mark A. Webster
发明人： Keith R. Baldwin , Mark A. Webster
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03D3/008 , H03L7/0812 , H03L7/085 , H04B1/30 , H04L25/061
摘要： A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture including a DC loop and a gain loop. The method includes processing energy in a wireless medium to generate a corresponding receive signal, monitoring the receive signal via a predetermined measurement window, detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop in an attempt to search a stable DC value for the receive signal while the gain loop is held constant. A first case is DC saturation, where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet. A third case is preparation for receiving an expected acknowledgement packet after transmitting a packet, where again a prior stored gain setting is applied to the gain loop and DC is searched.
摘要翻译：一种控制在包括DC环路和增益环路的零中频架构中配置的无线设备的操作的方法。该方法包括处理无线介质中的能量以产生相应的接收信号，经由预定的测量窗口监测接收信号，检测信道中的改变的状态，将增益反馈控制环保持在恒定的增益水平，以及操作DC 在增益环保持恒定的同时尝试搜索稳定的DC值作为接收信号。第一种情况是DC饱和，其中增益保持恒定，直到DC被控制。第二种情况是清除信道评估，其中在检测到分组的结束之后，将先前存储的增益设置应用于增益环路。第三种情况是在发送分组之后接收预期确认分组的准备，其中再次将先前存储的增益设置应用于增益循环并且搜索DC。

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