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1. 发明授权

US5661086A Process for manufacturing a plurality of strip lead frame semiconductor devices 失效
标题翻译：用于制造多个带状引线框半导体器件的工艺
公开(公告)号：US5661086A
公开(公告)日：1997-08-26
申请号：US584299
申请日：1996-01-11
申请人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
发明人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
IPC分类号： H01L21/48 , H01L23/13 , H01L23/31 , H01L23/498 , H01L21/52 , H01L21/58 , H01L21/60
CPC分类号： H01L23/49811 , H01L21/4803 , H01L21/4846 , H01L23/13 , H01L23/3128 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , Y10T29/49121
摘要： Method for producing semiconductor devices comprises a first step in which a plurality of metal substrates each of which is provided with a die mounting region at a central portion thereof are connected in series to produce a train of connected metal substrates by means of first connecting tabs and a pair of first side rails each of which is provided with first positioning pilot apertures are connected to the train by means of second connecting tabs to produce a metal substrate frame, a second step in which a plurality of circuit substrates each of which is provided with a lead pattern around an opening formed at the central portion thereof are connected in series by means of third connecting tabs to produce a train of connected circuit substrates and a pair of second side rails each of which is provided with second positioning pilot apertures are connected by fourth connecting tabs to produce a circuit substrate frame, a third step in which both frames are alinged with each other making use of the first and second positioning pilot apertures and are adhered with each other to produce a die mounting substrate frame, and a fourth step in which a semiconductor die is received in a cavity defined by the die mounting region and the opening of each die mounting substrate and solder balls are connected to terminal pads which form one ends of the lead pattern while pads of the semiconductor die are connected to wire bonding pads which form other ends of the lead pattern, and connecting tabs are removed so as to produce separate semiconductor devices.
摘要翻译：用于制造半导体器件的方法包括：第一步骤，其中在其中心部分设置有管芯安装区域的多个金属基板串联连接，以通过第一连接突片和一对第一侧轨，每个第一侧轨设置有第一定位导向孔，通过第二连接翼连接到列上，以产生金属基底框架;第二步，其中多个电路基板设置有围绕其中心部分形成的开口周围的引线图案通过第三连接突片串联连接，以产生一系列连接的电路基板和一对第二侧轨，每个第二侧轨设置有第二定位导向孔，第四连接片以产生电路衬底框架，第三步骤，其中两个框架彼此相互嵌合使用第一和第二定位导向孔并彼此粘合以产生模具安装基板框架，以及第四步骤，其中半导体管芯被容纳在由管芯安装区域和每个管芯的开口限定的空腔中安装基板和焊球连接到形成引线图案的一端的端子焊盘，而半导体管芯的焊盘连接到形成引线图案的另一端的引线接合焊盘，并且连接接线片被移除以产生单独的半导体设备。

2. 发明申请

US20070181983A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070181983A1
公开(公告)日：2007-08-09
申请号：US11501325
申请日：2006-08-09
申请人： Keiji Takai , Tetsuyuki Hirashima
发明人： Keiji Takai , Tetsuyuki Hirashima
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/4832 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2221/68377 , H01L2224/0401 , H01L2224/05599 , H01L2224/16 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85464 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2224/45099 , H01L2924/00012
摘要： A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadframe material 10, and the leadframe material 10 is consecutively subjected to etching by using the plating mask 38, 39 as a resist mask, so as to form external connection terminal portions 22 which electrically communicate with a semiconductor element 18 disposed in an interior of an encapsulating resin 21, and which project downwardly. Base metal plating or noble metal plating 33 exhibiting etching solution resistance is provided as a lowermost layer of the plating mask 38, 39.
摘要翻译：一种制造半导体器件28的方法，其中在引线框架材料10的正面或反面侧上的预定部分处形成具有作为最上层的贵金属镀层35的电镀掩模38,39，以及引线框架材料10通过使用电镀掩模38,39作为抗蚀剂掩模连续地进行蚀刻，以便形成与设置在封装树脂21的内部的半导体元件18电连通的外部连接端子部分22，以及向下突出。作为电镀掩模38,39的最下层，提供显示抗蚀剂电阻的基底金属电镀或贵金属电镀33。

3. 发明授权

US06659385B2 Wire-winding machine and a wire-winding method for making windings of a rotary electromechanical device 失效
公开(公告)号：US06659385B2
公开(公告)日：2003-12-09
申请号：US09922686
申请日：2001-08-07
申请人： Hiroyuki Akita , Yuji Nakahara , Nobuaki Miyake , Kazuya Omura , Keiji Takai , Kazunari Tomita , Naoki Kawasugi
发明人： Hiroyuki Akita , Yuji Nakahara , Nobuaki Miyake , Kazuya Omura , Keiji Takai , Kazunari Tomita , Naoki Kawasugi
IPC分类号： H02K15085
CPC分类号： H02K15/095
摘要： A wire-winding machine for forming coils (20) on individual magnetic pole teeth (11a) of a core member (13) which is produced by joining a plurality of core segments (11), each of the core segments (11) having a yoke portion (11c) and a magnetic pole tooth (11a) projectingly formed on an inside surface (11d) of the yoke portion (11c), comprises a core member positioner including a rotating roller (14), large-diameter guide rollers (21) and small-diameter guide rollers (22) which together serve to bend the core member (13) and hold it in a position where the core segments (11.3, 11.5) adjacent to the core segment (11.4) on which the coil (20) is currently wound do not project in the direction of its magnetic pole tooth (11a) beyond a boundary surface (S) of the yoke portion (11c) of the core segment (11.4) on which the coil (20) is currently wound.

4. 发明授权

US5614443A Method of producing a frame made of connected semiconductor die mounting substrates 失效
标题翻译：制造由连接的半导体管芯安装基板制成的框架的方法
公开(公告)号：US5614443A
公开(公告)日：1997-03-25
申请号：US622144
申请日：1996-03-27
申请人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
发明人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
IPC分类号： H01L23/12 , H01L21/98 , H01L23/50 , H01L23/538 , H01L25/065 , H01L21/60
CPC分类号： H01L25/50 , H01L23/5385 , H01L25/0655 , H01L2924/0002 , Y10T156/1057 , Y10T29/4921 , Y10T29/49222
摘要： Method of producing a frame made of connected semiconductor die mounting substrates comprises i) a first step for producing a metal substrate sheet wherein an original material for metal substrate sheet of a desired size is cut out from a metal material and an erosion preventing layer is provided on the entire surface thereof, ii) a second step for producing a circuit substrate sheet wherein the circuit substrate sheet is made of a resin substrate coated with a copper leaf layer and is provided with a lead pattern on the surface thereof in place, iii) a third step for producing a connected semiconductor die mounting substrate sheet by adhering the metal substrate sheet to the circuit substrate sheet, iv) a fourth step for forming a plurality of pilot apertures and slits on the connected semiconductor die mounting substrate sheet by press working and v) a fifth step for producing a plurality of connected semiconductor die mounting substrate frames by separating the connected semiconductor die mounting substrate sheet.
摘要翻译：制造由连接的半导体管芯安装基板制成的框架的方法包括：i）制造金属基片的第一步骤，其中提供从金属材料切割所需尺寸的金属基片的原始材料和防腐蚀层在其整个表面上，ii）用于制造电路基片的第二步骤，其中电路基片由涂有铜箔层的树脂基片制成，并在其表面上设有引线图案，iii）第三步骤，通过将金属基片粘附到电路基片上来制造连接的半导体管芯安装基片; iv）第四步骤，用于通过冲压加工在连接的半导体管芯安装基片上形成多个引导孔和狭缝， v）通过分离连接的半导体来生产多个连接的半导体管芯安装衬底框架的第五步骤或模具安装基板。

5. 发明授权

US4477447A 7-Acylaminocephalosporanic acid derivatives 失效
标题翻译： 7-酰氨基头孢烷酸衍生物
公开(公告)号：US4477447A
公开(公告)日：1984-10-16
申请号：US351858
申请日：1982-02-24
申请人： Ikuo Ueda , Tsutomu Teraji , Takao Takaya , Keiji Takai , Hisashi Takasugi , Fumio Shimojo , Shigetaka Nishino
发明人： Ikuo Ueda , Tsutomu Teraji , Takao Takaya , Keiji Takai , Hisashi Takasugi , Fumio Shimojo , Shigetaka Nishino
IPC分类号： A61K20060101 , A61K31/545 , C07D20060101 , C07D501/14 , C07D501/16 , C07D501/20 , C07D501/22 , C07D501/46 , C07D501/60
CPC分类号： C07D501/20
摘要： This invention relates to novel 7-acylaminocephalosporanic acid derivatives of high antimicrobial activity, to processes for their preparation, and to pharmaceutical compositions comprising said derivatives, said derivatives being of the formula: ##STR1## wherein R.sup.1 is amino or protected amino,R.sup.2 is dialkanoyloxy(lower)alkyl; alkyl having one or more substituents selected from the group consisting of hydroxy, protected hydroxy, alkoxy, carboxy, protected carboxy, cycloalkylcarbonyloxy and heterocyclic group; lower alkoxycarbonyloxy(lower)alkyl; azido(lower)alkoxycarbonyloxy(lower)alkyl; aroyloxy(lower)alkyl; higher alkanoyloxy(lower)alkyl; phthalidyl; or phthalidylidene(lower)alkyl,R.sup.3 is lower alkyl,Y is thio (--S--) or sulfinyl (--S--), and the dotted line represents 2- or 3-cephem nuclei.
摘要翻译：本发明涉及高抗微生物活性的新型7-酰基氨基头孢烷酸衍生物及其制备方法，以及包含所述衍生物的药物组合物，所述衍生物具有下式：其中R1是氨基或被保护的氨基，R2是二烷酰氧基（低级）烷基; 具有一个或多个选自羟基，保护的羟基，烷氧基，羧基，保护的羧基，环烷基羰基氧基和杂环基的取代基的烷基; 低级烷氧基羰氧基（低级）烷基; 叠氮基（低级）烷氧基羰氧基（低级）烷基; 芳氧基（低级）烷基; 高级烷酰氧基（低级）烷基; 苯酞; 或低级烷基，R 3为低级烷基，Y为硫代（-S-）或亚磺酰基（-S-），虚线表示2-或3-头孢烯核。

6. 发明申请

US20110095405A1 LEAD FRAME AND INTERMEDIATE PRODUCT OF SEMICONDUCTOR DEVICE 有权
标题翻译：导线框架和半导体器件的中间产品
公开(公告)号：US20110095405A1
公开(公告)日：2011-04-28
申请号：US12911212
申请日：2010-10-25
申请人： Keiji TAKAI
发明人： Keiji TAKAI
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/85444 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.
摘要翻译：在用于制造半导体器件的引线框架中，通过形成一个电路图案组，该电路图案组包括在一行或多行半导体元件安装区域的周围具有多个上侧端子部分的单元引线框架和围绕电路图案组的外框架在引线框材料具有间隙的状态下，然后在每个单元引线框架上安装半导体元件并且执行必要的布线并且封装其中安装半导体元件的电路图案组的整个表面，并且部分具有来自上表面侧的树脂的外框架，并且进一步从下表面侧进行蚀刻，并且形成接合到电路图案组，电路图案组和外框架的上侧端子部分的下侧端子部分，并且内框架外框架的边缘在平面图中形成为不平坦部分，并且增强了树脂和外框架之间的接合。

7. 发明授权

US08258608B2 Lead frame and intermediate product of semiconductor device 有权
标题翻译：半导体器件的引线框架和中间产品
公开(公告)号：US08258608B2
公开(公告)日：2012-09-04
申请号：US12911212
申请日：2010-10-25
申请人： Keiji Takai
发明人： Keiji Takai
IPC分类号： H01L21/02
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/85444 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.
摘要翻译：在用于制造半导体器件的引线框架中，通过形成一个电路图案组，该电路图案组包括在一行或多行半导体元件安装区域的周围具有多个上侧端子部分的单元引线框架和围绕电路图案组的外框架在引线框材料具有间隙的状态下，然后在每个单元引线框架上安装半导体元件并且执行必要的布线并且封装其中安装半导体元件的电路图案组的整个表面，并且部分具有来自上表面侧的树脂的外框架，并且进一步从下表面侧进行蚀刻，并且形成接合到电路图案组，电路图案组和外框架的上侧端子部分的下侧端子部分，并且内框架外框架的边缘在平面图中形成为不平坦部分，并且增强了树脂和外框架之间的接合。

8. 发明授权

US08003444B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08003444B2
公开(公告)日：2011-08-23
申请号：US11501325
申请日：2006-08-09
申请人： Keiji Takai , Tetsuyuki Hirashima
发明人： Keiji Takai , Tetsuyuki Hirashima
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2221/68377 , H01L2224/0401 , H01L2224/05599 , H01L2224/16 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85464 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2224/45099 , H01L2924/00012
摘要： A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadframe material 10, and the leadframe material 10 is consecutively subjected to etching by using the plating mask 38, 39 as a resist mask, so as to form external connection terminal portions 22 which electrically communicate with a semiconductor element 18 disposed in an interior of an encapsulating resin 21, and which project downwardly. Base metal plating or noble metal plating 33 exhibiting etching solution resistance is provided as a lowermost layer of the plating mask 38, 39.
摘要翻译：一种制造半导体器件28的方法，其中在引线框架材料10的正面或反面侧上的预定部分处形成具有作为最上层的贵金属镀层35的电镀掩模38,39，以及引线框架材料10通过使用电镀掩模38,39作为抗蚀剂掩模连续地进行蚀刻，以便形成与设置在封装树脂21的内部的半导体元件18电连通的外部连接端子部分22，以及向下突出。作为电镀掩模38,39的最下层，提供显示抗蚀剂电阻的基底金属电镀或贵金属电镀33。

9. 发明授权

US5717252A Solder-ball connected semiconductor device with a recessed chip mounting area 失效
标题翻译：焊球连接的半导体器件具有凹陷的芯片安装区域
公开(公告)号：US5717252A
公开(公告)日：1998-02-10
申请号：US757639
申请日：1996-12-02
申请人： Takashi Nakashima , Atsushi Fukui , Keiji Takai , Koji Tateishi
发明人： Takashi Nakashima , Atsushi Fukui , Keiji Takai , Koji Tateishi
IPC分类号： H01L23/13 , H01L23/31 , H01L23/498 , H01L23/34
CPC分类号： H01L23/3128 , H01L23/13 , H01L23/49816 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： A semiconductor device which remains highly reliable and is easy to mount even when a bonding pad pitch is reduced. The semiconductor device is featured in that a thermally conductive support substrate in which a semiconductor chip is fixed to a recessed portion is mounted on the reverse side of an insulating tape, that is, a TAB substrate having a conductor pattern on the surface; and solder balls are placed on the front side of the insulating tape to ensure connection to the conductor pattern on the front side through holes.
摘要翻译：一种半导体器件，其保持高可靠性并且即使当焊盘间距减小时也容易安装。半导体器件的特征在于，在绝缘带的背面安装有将半导体芯片固定到凹部的导热性支撑基板，即表面具有导体图案的TAB基板; 并且焊球放置在绝缘带的前侧，以确保连接到前侧通孔的导体图案。

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