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1. 发明申请

US20110223730A1 METHOD OF MANUFACTURING SEMICONDUCTOR CIRCUIT DEVICE 有权
标题翻译：制造半导体电路器件的方法
公开(公告)号：US20110223730A1
公开(公告)日：2011-09-15
申请号：US13046098
申请日：2011-03-11
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： H01L21/8242
CPC分类号： H01L27/0629
摘要： Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor film, and a second polysilicon film, reduction in resistance of a normally-off transistor and reduction in resistance of a lower electrode of the capacitor are simultaneously performed, and reduction in resistance of an N-type MOS transistor and reduction in resistance of an upper electrode of the capacitor are simultaneously performed.
摘要翻译：提供一种制造半导体电路器件的方法，该半导体电路器件包括MOS晶体管和电容器元件，其中MOS晶体管的栅电极由第一多晶硅膜形成，电容器由第一多晶硅膜，电容器膜和同时执行第二多晶硅膜，常规截止晶体管的电阻降低和电容器的下电极的电阻降低，并且N型MOS晶体管的电阻降低和上电极的电阻降低电容器同时进行。

2. 发明申请

US20100208532A1 MEMORY CIRCUIT 有权
标题翻译：存储器电路
公开(公告)号：US20100208532A1
公开(公告)日：2010-08-19
申请号：US12701144
申请日：2010-02-05
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： G11C7/00 , G11C8/10 , G11C7/10
CPC分类号： G11C29/02 , G11C7/20 , G11C17/143 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/028
摘要： Provided is a memory circuit including: memory cells (A) arranged in columns and rows; memory cells (B) each provided for each of the rows for storing information indicative of whether writing into the memory cells (A) of the each of the rows has been completed or not; and a circuit for selecting one of the rows by utilizing the information stored in the memory cells (B). The memory circuit writes information into the memory cell (B) upon completion of writing into the memory cells (A) of a given one of the rows. By utilizing a change in the information stored in the memory cell (B), the given one of the rows is switched from a selected state to a non-selected state, and a next row is switched from the non-selected state to the selected state so that writing is enabled. The operation is repeated to thereby sequentially select a row to be written.
摘要翻译：提供了一种存储电路，包括：列和列布置的存储单元（A）为每个行提供的存储单元（B），用于存储指示是否已经完成对每行的存储单元（A）的写入的信息; 以及通过利用存储在存储单元（B）中的信息来选择一行的电路。在写入给定行的存储单元（A）之后，存储电路将信息写入存储单元（B）。通过利用存储在存储单元（B）中的信息的改变，将给定的一行从选择状态切换到非选择状态，并且将下一行从未选择的状态切换到所选择的状态状态，以便启用写入。重复操作，从而顺序地选择要写入的行。

3. 发明申请

US20100046298A1 Non-volatile semiconductor memory circuit 有权
标题翻译：非易失性半导体存储器电路
公开(公告)号：US20100046298A1
公开(公告)日：2010-02-25
申请号：US12462910
申请日：2009-08-11
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/0416 , G11C5/147 , G11C16/10 , G11C16/26 , G11C16/30
摘要： Provided is a non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof by connecting a constant current circuit (1) and a non-volatile memory cell (2) in series, and setting a connection point therebetween to be an output, to thereby enable writing, in a reading mode or a retention mode, in the non-volatile memory cell (2) which is in a write state. The non-volatile semiconductor memory circuit includes: a power supply for data reading and retaining and a power supply for data rewriting which are provided independently; and a transistor (3) between the output and the power supply for data rewriting, in which the transistor (3) is brought into conduction state when data is rewritten.
摘要翻译：提供了一种非易失性半导体存储器电路，其能够通过串联连接恒流电路（1）和非易失性存储单元（2）来提高数据保持特性并减小其面积，并将它们之间的连接点设定为输出，从而能够在读取模式或保持模式下写入处于写入状态的非易失性存储单元（2）中。非易失性半导体存储电路包括：独立设置的用于数据读取和保持的电源和用于数据重写的电源; 以及用于数据重写的输出和电源之间的晶体管（3），其中当数据被重写时晶体管（3）进入导通状态。

4. 发明申请

US20070272964A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070272964A1
公开(公告)日：2007-11-29
申请号：US11805098
申请日：2007-05-21
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： H01L29/94
CPC分类号： H01L29/735 , H01L29/0657 , H01L29/0692 , H01L29/6625 , H01L29/73
摘要： Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.
摘要翻译：提供一种半导体器件，包括：硅衬底; 至少两个彼此间隔开的沟槽彼此平行，并且通过从其表面垂直蚀刻硅衬底而形成; 用于在其中至少埋入沟槽的底表面的电绝缘膜; 形成在位于两个沟槽之间的硅衬底的区域中的基极区域; 以及分别形成在沟槽的侧表面的部分上的发射极区域和集电极区域，位于绝缘膜上方的侧面的部分形成在基极区域中。

5. 发明申请

US20130082317A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY ELEMENT 有权
标题翻译：半导体存储器件和半导体存储器元件
公开(公告)号：US20130082317A1
公开(公告)日：2013-04-04
申请号：US13628135
申请日：2012-09-27
申请人： Naoto KOBAYASHI , Kazuhiro TSUMURA
发明人： Naoto KOBAYASHI , Kazuhiro TSUMURA
IPC分类号： H01L29/788 , H01L27/088
CPC分类号： H01L29/788 , H01L27/088 , H01L27/11521 , H01L27/11558 , H01L29/7885
摘要： A semiconductor memory element for writing by a drain-avalanche hot electron includes a MOS transistor having a first semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a floating gate provided on the first semiconductor layer through intermediation of an insulating film; a channel region formed in a surface of the first semiconductor layer under the floating gate; and a source region and a drain region of the first conductivity type provided on the first semiconductor layer so as to be in contact with the channel region in which the channel region has a distribution of at least two kinds of carrier densities.
摘要翻译：用于由漏 - 雪崩热电子写入的半导体存储元件包括MOS晶体管，其具有形成在第一导电类型的半导体衬底上的第二导电类型的第一半导体层; 通过绝缘膜设置在第一半导体层上的浮置栅极; 形成在所述浮置栅极下方的所述第一半导体层的表面的沟道区域; 以及设置在第一半导体层上的第一导电类型的源极区和漏极区，以与沟道区具有至少两种载流子密度分布的沟道区相接触。

6. 发明授权

US08274830B2 Constant current read mode or constant current data retention mode nonvolatile memory device 有权
标题翻译：恒流读取模式或恒流数据保持模式非易失性存储器件
公开(公告)号：US08274830B2
公开(公告)日：2012-09-25
申请号：US12462910
申请日：2009-08-11
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416 , G11C5/147 , G11C16/10 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof comprises a constant current circuit and a non-volatile memory cell connected in series. A connection point between the constant current source and the non-volatile memory cell is selected to be an output to thereby enable writing, in a reading mode or a retention mode, in the non-volatile memory cell which is in a write state. The non-volatile semiconductor memory circuit includes a power supply for data reading and retaining and a power supply for data rewriting which are provided independently, and a transistor connected between the output and the power supply for data rewriting, in which the transistor is brought into conduction state when data is rewritten.
摘要翻译：能够提高数据保持特性并减小其面积的非易失性半导体存储器电路包括串联连接的恒流电路和非易失性存储单元。恒定电流源和非易失性存储单元之间的连接点被选择为输出，从而使得能够以读取模式或保持模式在处于写入状态的非易失性存储单元中写入。非易失性半导体存储器电路包括用于数据读取和保持的电源以及独立提供的用于数据重写的电源，以及连接在输出和用于数据重写的电源之间的晶体管，其中晶体管被引入数据重写时的导通状态。

7. 发明授权

US08581316B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08581316B2
公开(公告)日：2013-11-12
申请号：US13409261
申请日：2012-03-01
申请人： Ayako Inoue , Kazuhiro Tsumura
发明人： Ayako Inoue , Kazuhiro Tsumura
IPC分类号： H01L27/108
CPC分类号： H01L27/0629
摘要： Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.

8. 发明申请

US20130016563A1 MEMORY CIRCUIT 有权
标题翻译：存储器电路
公开(公告)号：US20130016563A1
公开(公告)日：2013-01-17
申请号：US13534132
申请日：2012-06-27
申请人： Jun OSANAI , Yoshitsugu Hirose , Kazuhiro Tsumura , Ayake Inoue
发明人： Jun OSANAI , Yoshitsugu Hirose , Kazuhiro Tsumura , Ayake Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0441 , G11C16/26
摘要： Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.
摘要翻译：提供了在上电时不太可能发生错误写入的存储电路。存储器电路（10）包括：用于写入的P沟道非易失性存储元件（15），仅在写入期间在其源极和漏极之间施加电压以便写入数据; 和用于读取的N沟道非易失性存储器元件（16），其具有与P沟道非易失性存储元件（15）的控制栅极和浮置栅极共同设置的控制栅极和浮置栅极，以及仅在读取期间将电压施加到源极和漏极，以便读取数据。

9. 发明授权

US08259516B2 Memory circuit including row and column selection for writing information 有权
标题翻译：存储电路，包括行和列选择用于写入信息
公开(公告)号：US08259516B2
公开(公告)日：2012-09-04
申请号：US12701144
申请日：2010-02-05
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C29/02 , G11C7/20 , G11C17/143 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/028
摘要： Provided is a memory circuit including: memory cells (A) arranged in columns and rows; memory cells (B) each provided for each of the rows for storing information indicative of whether writing into the memory cells (A) of the each of the rows has been completed or not; and a circuit for selecting one of the rows by utilizing the information stored in the memory cells (B). The memory circuit writes information into the memory cell (B) upon completion of writing into the memory cells (A) of a given one of the rows. By utilizing a change in the information stored in the memory cell (B), the given one of the rows is switched from a selected state to a non-selected state, and a next row is switched from the non-selected state to the selected state so that writing is enabled. The operation is repeated to thereby sequentially select a row to be written.
摘要翻译：提供了一种存储电路，包括：列和列布置的存储单元（A）为每个行提供的存储单元（B），用于存储指示是否已经完成对每行的存储单元（A）的写入的信息; 以及通过利用存储在存储单元（B）中的信息来选择一行的电路。在写入给定行的存储单元（A）之后，存储电路将信息写入存储单元（B）。通过利用存储在存储单元（B）中的信息的改变，将给定的一行从选择状态切换到非选择状态，并且将下一行从未选择的状态切换到所选择的状态状态，以便启用写入。重复操作，从而顺序地选择要写入的行。

10. 发明授权

US07902633B2 Longitudinal bipolar transistor with base region in trenches having emitter and collector regions disposed along portions of side surfaces of the base 有权
标题翻译：纵向双极晶体管，其沟槽中具有基极区域，其中发射极和集电极区域沿基底的侧表面的部分设置
公开(公告)号：US07902633B2
公开(公告)日：2011-03-08
申请号：US11805098
申请日：2007-05-21
申请人： Kazuhiro Tsumura
发明人： Kazuhiro Tsumura
IPC分类号： H01L29/73
CPC分类号： H01L29/735 , H01L29/0657 , H01L29/0692 , H01L29/6625 , H01L29/73
摘要： Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.
摘要翻译：提供一种半导体器件，包括：硅衬底; 至少两个彼此间隔开的沟槽彼此平行，并且通过从其表面垂直蚀刻硅衬底而形成; 用于在其中至少埋入沟槽的底表面的电绝缘膜; 形成在位于两个沟槽之间的硅衬底的区域中的基极区域; 以及分别形成在沟槽的侧表面的部分上的发射极区域和集电极区域，位于绝缘膜上方的侧面的部分形成在基极区域中。

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