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1. 发明授权

US06225577B1 Co-ordinates input device and a method for producing the same 失效
标题翻译：坐标输入装置及其制造方法
公开(公告)号：US06225577B1
公开(公告)日：2001-05-01
申请号：US09015348
申请日：1998-01-29
申请人： Katsunori Sawai , Hideto Sasagawa , Takeshi Watanabe , Takayuki Ito
发明人： Katsunori Sawai , Hideto Sasagawa , Takeshi Watanabe , Takayuki Ito
IPC分类号： G08C2100
CPC分类号： G06F3/045
摘要： A co-ordinates input device having a transparent substrate member is composed of: a transparent substrate; an ITO film formed on a surface of the transparent substrate; a pair of electrodes formed at a given distance from each other on the ITO film; an operation region formed between the pair of electrodes; and lead electrodes, extending from the pair of electrodes, formed on the ITO film; in which at least one of the lead electrodes extending from the pair of electrodes is formed on the ITO film on a side of the operation region, and between the lead electrode and the operation region, a groove is formed in the ITO film alone or in the ITO film and continuously extending into the transparent substrate.
摘要翻译：具有透明基板部件的坐标输入装置由透明基板构成，形成在所述透明基板的表面上的ITO膜; 在ITO膜上以一定距离彼此形成的一对电极; 形成在所述一对电极之间的操作区域; 以及从形成在ITO膜上的一对电极延伸的引线电极; 其中从一对电极延伸的至少一个引出电极形成在操作区域侧的ITO膜上，并且在引线电极和操作区域之间，在ITO膜中单独地或在 ITO膜并连续延伸到透明基板中。

2. 发明授权

US06308195B1 4-2 compressor circuit and voltage holding circuit for use in 4-2 compressor circuit 失效
标题翻译： 4-2压缩机电路和电压保持电路用于4-2压缩机电路
公开(公告)号：US06308195B1
公开(公告)日：2001-10-23
申请号：US09248284
申请日：1999-02-11
申请人： Yuko Hirase , Katsunori Sawai
发明人： Yuko Hirase , Katsunori Sawai
IPC分类号： G06F750
CPC分类号： G06F7/5338 , G06F7/607
摘要： A 4-2 compressor circuit calculates the sum of first through fourth inputs and a carry input applied thereto and for furnishing the summation result and first and second carries generated during the calculation of the summation. An input value converting unit inverts the third and fourth inputs only if the third input is logic 0 and the fourth input is logic 1. A summation unit calculates the logical exclusive OR of any two of the first through fourth inputs and the carry input applied to the 4-2 compressor circuit, the logical exclusive OR of any two of the first logical exclusive OR and the remaining three inputs, the logical exclusive OR of any two of the second logical exclusive OR and the remainder, and the logical exclusive OR of the third logical exclusive OR and the remainder. The summation unit then furnishes the fourth logical exclusive OR as the summation result. A carry calculating unit calculates the first carry from the first, third, and fourth inputs. A selecting unit selects either the carry input or the second input according to the logical exclusive OR of the logical exclusive OR of any two of the first through fourth inputs and the logical exclusive OR of the remainder, and then furnishes the selected one as the second carry.
摘要翻译： 4-2压缩机电路计算第一至第四输入和应用于其的进位输入的和，并且用于提供求和结果和在求和的计算期间产生的第一和第二输入。输入值转换单元仅在第三输入为逻辑0且第四输入为逻辑1时反转第三和第四输入。求和单元计算第一至第四输入中的任何两个的逻辑异或或应用于 4-2压缩器电路，第一逻辑异或和其余三个输入中的任何两个的逻辑异或，第二逻辑异或和余数中的任何两个的逻辑异或，以及逻辑异或第三个逻辑异或OR和其余。求和单元然后提供第四逻辑异或作为求和结果。进位计算单元从第一，第三和第四输入端计算第一进位。选择单元根据第一至第四输入中的任意两个的逻辑异或与余数的逻辑异或逻辑异或运算来选择进位输入或第二输入，然后将所选择的逻辑异或携带。

3. 发明授权

US5915099A Bus interface unit in a microprocessor for facilitating internal and external memory accesses 失效
标题翻译：微处理器中的总线接口单元，用于便于内部和外部存储器访问
公开(公告)号：US5915099A
公开(公告)日：1999-06-22
申请号：US803858
申请日：1997-02-21
申请人： Yukari Takata , Mitsugu Satou , Hiroyuki Kondo , Katsunori Sawai
发明人： Yukari Takata , Mitsugu Satou , Hiroyuki Kondo , Katsunori Sawai
IPC分类号： G06F13/36 , G06F13/16 , G06F13/40 , G06F15/78 , G06F13/00
CPC分类号： G06F13/1605 , G06F13/4027
摘要： In a microprocesssor (101), a selector (7) is connected to a bus ID through a write buffer (5) and a DRAM (27), a cache (28) and an IQ (8) are also connected to the bus ID . The bus ID and the microprocessor (101) are connected to the external memory (4) and the external bus master (41) with a data bus D through a BIU (3). The microprocessor (101) is also connected to the external memory (4) and the external bus master (41) with an address bus (58) and control bus (57). The BIU (3) controls an access to a memory integrated in the microprocessor (101) and a memory externally connected thereto. With this configuration, the DRAM and the cache can be integrated together in the microprocessor which is externally connected to the bus master.
摘要翻译：在微处理器（101）中，选择器（7）通过写缓冲器（5）和DRAM（27），高速缓存（28）和IQ（8）连接到总线ID <0：127> 连接到总线ID <0：127>。总线ID <0：127>和微处理器（101）通过BIU（3）与数据总线D <0:15>连接到外部存储器（4）和外部总线主机（41）。微处理器（101）也用地址总线（58）和控制总线（57）连接到外部存储器（4）和外部总线主机（41）。 BIU（3）控制对集成在微处理器（101）中的存储器和外部与其连接的存储器的访问。利用这种配置，DRAM和高速缓存可以集成在外部连接到总线主机的微处理器中。

4. 发明授权

US5165029A Cache memory with test function 失效
标题翻译：具有测试功能的缓存内存
公开(公告)号：US5165029A
公开(公告)日：1992-11-17
申请号：US558929
申请日：1990-07-27
申请人： Katsunori Sawai , Akira Yamada
发明人： Katsunori Sawai , Akira Yamada
IPC分类号： G06F12/08 , G06F12/16 , G11C29/52
CPC分类号： G06F12/0888 , G11C29/52
摘要： A cache memory, which is provided with means for prohibiting generation of an external bus cycle to read the data to be accessed from a main storage and means for prohibiting update of the content of a tag memory when a cache miss is generated under a test mode of its test function in order to shorten the test time by omitting the process of resetting test patterns in both the tag memory and a data memory.
摘要翻译：一种缓存存储器，其具有用于禁止生成外部总线周期以从主存储器读取要访问的数据的装置，以及用于在测试模式下生成高速缓存未命中时禁止更新标签存储器的内容的装置的测试功能，以便通过省略标签存储器和数据存储器中复位测试模式的过程来缩短测试时间。

5. 发明授权

US5787310A Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US5787310A
公开(公告)日：1998-07-28
申请号：US500039
申请日：1995-07-10
申请人： Toru Shimizu , Katsunori Sawai , Yukihiko Shimazu , Masaki Kumanoya , Katsumi Dosaka
发明人： Toru Shimizu , Katsunori Sawai , Yukihiko Shimazu , Masaki Kumanoya , Katsumi Dosaka
IPC分类号： G06F13/00 , G06F13/16 , G06F15/78 , G06F9/02 , G06F9/06 , G06F12/06
CPC分类号： G06F15/7842 , G06F13/1684
摘要： A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.
摘要翻译：一种微处理器，包括处理器和集成在一个芯片上的存储器，其中存储器被布置在多个存储单元区域行中，并且处理器被布置在存储单元区域行之间。一种微型计算机，其中存储单元区域通过每个连接到处理器的总线逐行连接。

6. 发明授权

US6049238A Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements 失效
标题翻译：时钟发生器和时钟产生方法能够改变时钟频率而不增加延迟元件的数量
公开(公告)号：US6049238A
公开(公告)日：2000-04-11
申请号：US178580
申请日：1998-10-26
申请人： Kazuyoshi Shimizu , Kouichi Ishimi , Katsunori Sawai
发明人： Kazuyoshi Shimizu , Kouichi Ishimi , Katsunori Sawai
IPC分类号： H03K3/027 , H03K3/86 , H03L7/06 , H03L7/08 , H03L7/181
CPC分类号： H03K3/027 , H03K3/86 , H03L7/06 , H03L7/08 , H03L7/181
摘要： A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock. This can reduce the phase difference between the input clock and the phase-locked clock, and hence to solve a problem of a conventional clock generator in that a delay time of a digital delay line in a phase lock circuit must be lengthened with a reduction in the multiplication number of the frequency multiplied clock, which requires a greater number of delay elements because of a large occupying area of the delay elements and a decoder, thereby increasing the circuit scale and cost of a chip to reduce the multiplication number of the frequency multiplied clock.
摘要翻译：包括倍频器，锁相电路和分频器的时钟发生器。倍频器通过乘以输入时钟的频率来产生倍频时钟。锁相电路检测输入时钟和分频时钟之间的相位差，并通过将倍频时钟延迟与相位差对应的量来产生锁相时钟，其锁相与输入时钟相锁相。分频器在每个固定周期内检测锁相时钟的特定脉冲，并通过相对于锁相时钟的特定脉冲对相位锁定时钟进行分频来产生分频时钟。特别地，分频器检测紧接在输入时钟下降沿之前的特定脉冲。这可以减小输入时钟和锁相时钟之间的相位差，因此解决传统的时钟发生器的问题在于，锁相电路中的数字延迟线的延迟时间必须延长，同时减少频率倍增时钟的倍数，由于延迟元件的占用面积大，解码器需要较大数量的延迟元件，从而增加了芯片的电路规模和成本，从而减少倍频的倍数时钟。

7. 发明授权

US5801559A Clock generating circuit, PLL circuit, semiconductor device, and methods for designing and making the clock generating circuit 失效
标题翻译：时钟发生电路，PLL电路，半导体器件，以及用于设计和制造时钟发生电路的方法
公开(公告)号：US5801559A
公开(公告)日：1998-09-01
申请号：US588934
申请日：1996-01-19
申请人： Katsunori Sawai , Yukihiko Shimazu
发明人： Katsunori Sawai , Yukihiko Shimazu
IPC分类号： G06F1/10 , G11C11/407 , H03K3/02 , H03K5/00 , H03K5/135 , H03L7/081 , H03L7/087 , H03L7/16 , H03L7/18 , H03L7/00
CPC分类号： G06F1/10 , H03K5/135 , H03L7/0814 , H03L7/087 , H03L7/16
摘要： A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from: K>�{1/(2.multidot.N.multidot.F.sub.ref)}-(T.sub.mul)!/(T.sub.dmin)
摘要翻译：时钟发生电路包括串联连接的多个延迟线，每个延迟线包括两个用于允许或关闭时钟的开关元件，以及连接到每个开关元件的延迟元件。 PLL电路和半导体器件都包括时钟发生电路。时钟发生电路的每个延迟线中的延迟单元的数量K由下式计算：K> [{1 /（2xNxFref）} - （Tmul）] /（Tdmin）

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