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1. 发明申请

US20130126927A1 SEMICONDUCTOR LIGHT EMITTING DEVICE 有权
标题翻译：半导体发光器件
公开(公告)号：US20130126927A1
公开(公告)日：2013-05-23
申请号：US13682224
申请日：2012-11-20
申请人： Katsuji IGUCHI
发明人： Katsuji IGUCHI
IPC分类号： H01L33/60
CPC分类号： H01L33/60 , H01L33/58 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014
摘要： A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.
摘要翻译：半导体发光器件包括其上形成有布线图案的基板和安装在基板的一个主表面上并电连接到布线图案的半导体发光元件。基板在一个主表面上具有将从所述半导体发光元件发射的至少一部分光反射到基板的锯齿状结构，该垂直于该主表面的方向。

2. 发明授权

US6153460A Method of fabricating semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US6153460A
公开(公告)日：2000-11-28
申请号：US470990
申请日：1999-12-23
申请人： Shigeo Ohnishi , Nobuyuki Takenaka , Katsuji Iguchi
发明人： Shigeo Ohnishi , Nobuyuki Takenaka , Katsuji Iguchi
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/8234
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method of fabricating a semiconductor memory device comprises the steps of: (a) forming an interlayer insulating film on a semiconductor substrate, opening a contact hole in said interlayer insulating film, and burying a plug in said contact hole; (b) forming a first insulating film on said interlayer insulating film inclusive of said plug, and forming a trench in said first insulating film above said plug; (c) forming a first conductive film on said first insulating film inclusive of said trench, and etching back said first conductive film by a chemical mechanical polishing method to form a bottom electrode inside said trench; (d) forming a high dielectric film or a ferroelectric film and a second conductive film in this order on said first insulating film inclusive of said bottom electrode; and (e) patterning simultaneously said high dielectric film or ferroelectric film and said second conductive film to form a capacitor insulating film and a top electrode.
摘要翻译：一种制造半导体存储器件的方法包括以下步骤：（a）在半导体衬底上形成层间绝缘膜，打开所述层间绝缘膜中的接触孔，并将插塞埋入所述接触孔中; （b）在包括所述插头的所述层间绝缘膜上形成第一绝缘膜，并且在所述插头上方的所述第一绝缘膜中形成沟槽; （c）在包括所述沟槽的所述第一绝缘膜上形成第一导电膜，并通过化学机械抛光方法蚀刻所述第一导电膜，以在所述沟槽内部形成底电极; （d）在包括所述底部电极的所述第一绝缘膜上依次形成高电介质膜或铁电体膜和第二导电膜; 和（e）同时形成所述高电介质膜或铁电体膜和所述第二导电膜以形成电容器绝缘膜和顶部电极。

3. 发明授权

US5493140A Nonvolatile memory cell and method of producing the same 失效
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US5493140A
公开(公告)日：1996-02-20
申请号：US262831
申请日：1994-06-21
申请人： Katsuji Iguchi
发明人： Katsuji Iguchi
IPC分类号： H01L21/336 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/4232
摘要： The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for the floating gate in conventional memory cells can be solved. In addition, the memory cells of the invention are suitable for device integration. Especially when the floating gate is formed of a polycrystalline silicon film, the device characteristics such as writing speed are remarkably improved.
摘要翻译：本发明的非易失性存储单元包括由超薄多晶硅膜形成的浮动栅极。由于存储单元包括具有光滑表面的这种超薄浮动栅极，因此可以解决在传统存储单元中浮动栅极图案化中出现的问题。此外，本发明的存储单元适合于器件集成。特别是当浮栅由多晶硅膜形成时，诸如写入速度的器件特性显着提高。

4. 发明授权

US5389474A Mask for photolithography 失效
标题翻译：光刻掩模
公开(公告)号：US5389474A
公开(公告)日：1995-02-14
申请号：US47056
申请日：1993-04-12
申请人： Katsuji Iguchi , Takashi Fukushima , Hiroki Tabuchi
发明人： Katsuji Iguchi , Takashi Fukushima , Hiroki Tabuchi
IPC分类号： G03F1/28 , G03F1/34 , G03F1/68 , H01L21/027 , H01L21/30 , G03F9/00
CPC分类号： G03F1/29
摘要： A mask for photolithography having a transparent substrate which allows light having a predetermined wavelength to pass therethrough; an opaque pattern provided on said substrate for inhibiting the light from passing therethrough; and a stepped portion provided adjacent to said opaque pattern on said substrate and having an inclined area, said stepped portion being transparent for allowing the light to pass therethrough, which can be used in a photolithographic system in fabrication of semiconductor devices and the like.
摘要翻译：一种用于光刻的掩模，具有允许具有预定波长的光通过的透明基板; 设置在所述基板上的用于抑制光通过的不透明图案; 以及设置在所述基板上与所述不透明图案相邻并且具有倾斜区域的阶梯部分，所述台阶部分是透明的，以允许光线通过，可用于制造半导体器件等的光刻系统中。

5. 发明授权

US06780700B2 Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide 失效
标题翻译：用MDD和选择性CVD硅化物制造深亚微米CMOS源/漏极的方法
公开(公告)号：US06780700B2
公开(公告)日：2004-08-24
申请号：US10035503
申请日：2001-10-25
申请人： Katsuji Iguchi , Sheng Teng Hsu , Yoshi Ono , Jer-shen Maa
发明人： Katsuji Iguchi , Sheng Teng Hsu , Yoshi Ono , Jer-shen Maa
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.
摘要翻译：一种在硅衬底上形成MOS器件或CMOS器件的方法，包括制备衬底以包含其中具有器件有源区的导电区; 在有源区上形成栅电极; 在每个栅电极上沉积和形成栅电极侧壁绝缘体层; 注入第一类型的离子以在一个有效区域中形成源极区域和漏极区域，并且注入第二类型的离子，以在另一个有源区域中形成源极区域和漏极区域。

6. 发明授权

US5795803A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5795803A
公开(公告)日：1998-08-18
申请号：US871680
申请日：1997-06-09
申请人： Yoshiji Takamura , Akio Kawamura , Katsuji Iguchi
发明人： Yoshiji Takamura , Akio Kawamura , Katsuji Iguchi
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A method of manufacturing a semiconductor device comprises; forming a device isolation region in a semiconductor substrate; forming at least a first conductivity type impurity region in the semiconductor substrate; and forming on the semiconductor substrate a transistor including a gate insulating film, a gate electrode, source/drain regions and a channel located directly under the gate electrode, wherein the first conductivity type impurity region is formed by the steps of: an ion implantation 1 having a concentration peak at a location deeper than the bottom of the device isolation region; an ion implantation 2 having a concentration peak at a location around the bottom of the device isolation region; an ion implantation 3 having a concentration peak around the junction regions where the source/drain regions are to be formed; and an ion implantation 4 having a concentration peak on the surface or directly under the surface of the region where the channel is to be formed.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底中形成器件隔离区; 在半导体衬底中形成至少第一导电型杂质区; 以及在所述半导体基板上形成包括栅极绝缘膜，栅极电极，源极/漏极区域和位于所述栅极电极正下方的沟道的晶体管，其中所述第一导电型杂质区域通过以下步骤形成：离子注入1 在比器件隔离区域的底部更深的位置处具有浓度峰值; 离子注入2，其在器件隔离区域的底部周围的位置处具有浓度峰值; 在要形成源/漏区的结区周围具有浓度峰的离子注入3; 以及在要形成沟道的区域的表面或表面下方具有浓度峰值的离子注入4。

7. 发明授权

US5734185A MOS transistor and fabrication process therefor 失效
标题翻译： MOS晶体管及其制造工艺
公开(公告)号：US5734185A
公开(公告)日：1998-03-31
申请号：US694067
申请日：1996-08-08
申请人： Katsuji Iguchi , Kenichi Azuma , Akio Kawamura
发明人： Katsuji Iguchi , Kenichi Azuma , Akio Kawamura
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/72 , H01L29/73
CPC分类号： H01L29/66568 , H01L21/26586 , H01L21/28114 , H01L21/28123 , H01L21/823814 , H01L21/82385 , H01L27/092 , H01L29/42376 , H01L29/66553 , H01L29/66583 , H01L29/66537
摘要： An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.
摘要翻译： MOS晶体管包括具有场区域的半导体衬底; 通过栅极绝缘膜的中间形成在半导体衬底上的栅电极; 以及形成在半导体衬底中的源/漏区; 其中所述场区域至少包括下绝缘膜和由允许所述上绝缘膜的材料制成的上绝缘膜相对于所述下绝缘膜选择性蚀刻; 所述栅电极被配置为使得其顶表面的栅极长度大于其面向位于所述源/漏区之间的沟道区的底表面的栅极长度; 所述栅电极具有由由所述下绝缘膜制成的侧壁绝缘层形成的侧壁间隔件和允许所述侧壁绝缘层相对于所述上绝缘膜选择性蚀刻的材料，所述侧壁间隔件与所述栅电极的侧壁接触用于覆盖通道区域的外围; 并且所述沟道区域与源极/漏极区域基本平齐。

8. 发明授权

US5576995A Method for rewriting a flash memory 失效
标题翻译：重写闪存的方法
公开(公告)号：US5576995A
公开(公告)日：1996-11-19
申请号：US547158
申请日：1995-10-24
申请人： Shinichi Sato , Katsuji Iguchi
发明人： Shinichi Sato , Katsuji Iguchi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/14
摘要： A method for rewriting a flash memory wherein a plurality of memory cells each of which comprises a pair of source and drain, a floating gate and a control gate are arranged in matrix in a first conductivity-type well formed in a second conductivity-type deep well formed in the first conductivity-type semiconductor substrate; and in which the floating gate is charged with electrons when the flash memory is written and the floating gate is discharged of the electrons when the flash memory is erased; in which the erasure of the flash memory is operated by applying to the first conductivity-type well a first positive voltage different from the potential of the substrate, applying to the source or the drain a second positive voltage higher than the first positive voltage and applying to the control gate a first negative voltage.
摘要翻译：一种用于重写闪速存储器的方法，其中包括一对源极和漏极的多个存储单元，浮置栅极和控制栅极以矩阵形式布置在形成于第二导电类型深度的第一导电型阱中在第一导电型半导体衬底中良好地形成; 并且当闪存被写入时浮置栅极被充电，并且当闪速存储器被擦除时浮置栅极被电子放电; 其中通过向第一导电类型阱施加不同于衬底的电位的第一正电压来操作闪速存储器的擦除，向源极或漏极施加高于第一正电压的第二正电压并施加向控制栅极施加第一负电压。

9. 发明授权

US5334869A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5334869A
公开(公告)日：1994-08-02
申请号：US112480
申请日：1993-08-27
申请人： Katsuji Iguchi , Seizo Kakimoto , Naoyuki Shinmura
发明人： Katsuji Iguchi , Seizo Kakimoto , Naoyuki Shinmura
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10844 , H01L27/10817 , Y10S438/947
摘要： A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor includes respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元包括形成在半导体衬底的表面上并具有一个端子的晶体管，以及形成在半导体衬底上并具有第一和第二电极的电容器，第一电极与一个第一电极连接晶体管的端子。电容器的第一电极包括大致矩形立方体形状或大致杯形构造的主要部分，与主要部分的周边侧壁间隔开并围绕主体部分的周边侧壁的周边部分，以及连接主体端部的底部部分该部分具有周边部分的端部。另一方面，电容器的第二电极包括与第一电极的主要部分，周边部分和底部相对的各个部分。

10. 发明授权

US5189501A Isolator for electrically isolating semiconductor devices in an integrated circuit 失效
标题翻译：用于电绝缘集成电路中的半导体器件的隔离器
公开(公告)号：US5189501A
公开(公告)日：1993-02-23
申请号：US841773
申请日：1992-03-02
申请人： Akio Kawamura , Katsuji Iguchi , Masahiko Urai
发明人： Akio Kawamura , Katsuji Iguchi , Masahiko Urai
IPC分类号： H01L21/762
CPC分类号： H01L21/76237
摘要： An isolator for isolating semiconductor devices, components of an integrated circuit, on a semiconductor substrate, wherein the isolator is delimited by walls of a trench formed on a top surface of the semiconductor substrate, and the trench is filled with a silicon oxide layer deposited by a chemical vapor deposition method. A small ditch created in the middle of a top surface of the silicon oxide layer in the trench is filled with silicon, and at least a top surface of the silicon is thermally oxidized to form another silicon oxide layer.
摘要翻译：一种在半导体衬底上隔离半导体器件（集成电路的部件）的隔离器，其中隔离器由在半导体衬底的顶表面上形成的沟槽的壁限定，并且该沟槽填充有由氧化硅层沉积的氧化硅层一种化学气相沉积法。在沟槽中的硅氧化物层的顶表面中间形成的小沟被硅填充，并且硅的至少顶表面被热氧化以形成另一氧化硅层。

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