专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06903598B2 Static, low-voltage fuse-based cell with high-voltage programming 有权
标题翻译：具有高压编程功能的静态，低电压熔丝式电池
公开(公告)号：US06903598B2
公开(公告)日：2005-06-07
申请号：US10155512
申请日：2002-05-24
申请人： Martin Spence Denham , Mohsen Alavi , Kaizad Rumy Mistry , Patrick John Ott , Rachael Jade Parker , Paul Gregory Slankard , Wenliang Chen
发明人： Martin Spence Denham , Mohsen Alavi , Kaizad Rumy Mistry , Patrick John Ott , Rachael Jade Parker , Paul Gregory Slankard , Wenliang Chen
IPC分类号： G06F1/03 , G06F7/48 , G06F7/52 , G06F7/523 , G06F7/57 , G11C17/16 , G11C17/18 , H01H37/76 , H01H85/00
CPC分类号： G11C17/18 , G11C17/16
摘要： A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.
摘要翻译：一个基于熔丝的电池。基于熔丝的电池包括具有电耦合到熔丝以对熔丝进行编程的编程装置的保险丝。感测装置电耦合到熔丝以感测熔丝的编程状态。夹紧装置电耦合到感测装置，以在编程期间控制感测装置两端的电压。通过装置电耦合到感测装置以在感测期间控制感测装置两端的电压。

2. 发明授权

US5821575A Compact self-aligned body contact silicon-on-insulator transistor 失效
标题翻译：紧凑的自对准体接触绝缘体上硅晶体管
公开(公告)号：US5821575A
公开(公告)日：1998-10-13
申请号：US650561
申请日：1996-05-20
申请人： Kaizad Rumy Mistry , Jeffrey William Sleight
发明人： Kaizad Rumy Mistry , Jeffrey William Sleight
IPC分类号： H01L21/84 , H01L27/12 , H01L29/78 , H01L27/108
CPC分类号： H01L29/78615 , H01L21/84 , H01L27/1203 , H01L29/7839
摘要： A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.
摘要翻译：一种场效应晶体管结构，其具有设置在绝缘体上并且已经形成在与第一类型相反的导电率的半导体的不同区域，源极区和漏极区中的第一类型的导电半导体本体，适于控制通过源极和漏极区域之间的半导体本体的沟道中的载流子流以及半导体本体与源极或漏极区之一之间的肖特基二极管接触区域。通过这样的布置，肖特基二极管在正向偏置时提供在半导体本体与源极或漏极区之一之间约0.3伏的固定电压。

3. 发明授权

US06352913B1 Damascene process for MOSFET fabrication 失效
标题翻译：用于MOSFET制造的镶嵌工艺
公开(公告)号：US06352913B1
公开(公告)日：2002-03-05
申请号：US09286185
申请日：1999-04-05
申请人： Kaizad Rumy Mistry , Lawrence Allen Bair
发明人： Kaizad Rumy Mistry , Lawrence Allen Bair
IPC分类号： H01L218238
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/823835 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/66583 , H01L29/6659
摘要： An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes on very thin gate oxide transistors are greatly improved, resulting in improved gate threshold voltage control and improved transistor electrical properties, without loss of the benefit of self aligned source and drain electrodes available with polysilicon gates. Dual metal gate electrodes are also disclosed and exhibit improved CMOS transistor function compared to polysilicon gates, resulting in better and more controlled transistor properties. Thus the metal Damascene gate process results in faster and more consistent MOS and CMOS transistors and improved IC fabrication.
摘要翻译：公开了一种改进的MOSFET晶体管，其具有高介电常数栅极电介质和金属栅电极。通过这样一个过程，非常薄的栅极氧化物晶体管上的多晶硅栅电极的已知问题大大改善，从而改善了栅极阈值电压控制和改进的晶体管电性能，而不损失可用于多晶硅的自对准源极和漏极的益处大门还公开了双金属栅电极，并且与多晶硅栅极相比表现出改进的CMOS晶体管功能，导致更好和更多受控的晶体管特性。因此，金属镶嵌栅极工艺可以实现更快，更一致的MOS和CMOS晶体管以及改进的IC制造。

4. 发明授权

US5930605A Compact self-aligned body contact silicon-on-insulator transistors 失效
标题翻译：紧凑的自对准体接触绝缘体上硅晶体管
公开(公告)号：US5930605A
公开(公告)日：1999-07-27
申请号：US895328
申请日：1997-07-16
申请人： Kaizad Rumy Mistry , Jeffrey William Sleight
发明人： Kaizad Rumy Mistry , Jeffrey William Sleight
IPC分类号： H01L21/84 , H01L27/12 , H01L29/78 , H01L27/095 , H01L29/812
CPC分类号： H01L29/78615 , H01L21/84 , H01L27/1203 , H01L29/7839
摘要： A field effect transistor structure having: a first type conductivity semiconductor body disposed on an insulator and having formed in different regions thereof: (a) a source region; (b) a drain region, such source and drain regions being of a conductivity type opposite the conductivity type of the body; (c) a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions; and (d) a Schottky contact region providing a Schottky diode between the semiconductor body and one of the source and drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 V, between the semiconductor body and one of the source and drain regions. A method for forming a semiconductor structure, comprising the steps of: providing a semiconductor body over an electrical insulator; providing source and drain areas in the semiconductor body on either side of a gate channel; introducing dopant into un-masked portions of the source and drain areas to form source and drain regions in the semiconductor body, such mask blocking such dopant from passing into the masked portion of at least one of the source and drain areas and the contiguous portion of the semiconductor body; and forming a metal between the masked portion of the at least one of the source and drain regions and the contiguous portion of the semiconductor body. The metal forming step may be performed prior to, or subsequent to, the dopant introduction step.
摘要翻译：一种场效应晶体管结构，具有：设置在绝缘体上并形成在其不同区域的第一类型的导电半导体本体：（a）源极区; （b）漏极区域，所述源极和漏极区域具有与所述主体的导电类型相反的导电类型; （c）栅极电极，适于控制通过源极和漏极区域之间的半导体本体的沟道中的载流子流; 和（d）在半导体本体与源极和漏极区之一之间提供肖特基二极管的肖特基接触区域。通过这样的布置，肖特基二极管在正向偏压时提供在半导体本体与源极和漏极区之一之间约0.3V的固定电压。一种用于形成半导体结构的方法，包括以下步骤：在电绝缘体上提供半导体本体; 在栅极通道的任一侧的半导体本体中提供源极和漏极区域; 将掺杂剂引入到源极和漏极区域的未掩蔽部分中以在半导体主体中形成源极和漏极区域，这种掩模阻挡这种掺杂剂进入源极和漏极区域中的至少一个的屏蔽部分，并且邻接部分半导体体; 以及在所述源极和漏极区域中的至少一个的所述掩蔽部分和所述半导体本体的所述连续部分之间形成金属。金属形成步骤可以在掺杂剂引入步骤之前或之后进行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式