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1. 发明申请

US20130015571A1 Semiconductor Package And Method Of Manufacturing The Same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20130015571A1
公开(公告)日：2013-01-17
申请号：US13479971
申请日：2012-05-24
申请人： Jung Hwan CHUN
发明人： Jung Hwan CHUN
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/14 , H01L24/17 , H01L24/73 , H01L24/92 , H01L25/074 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92242 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06572 , H01L2924/01029 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/0665 , H01L2224/81
摘要： A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.
摘要翻译：半导体封装及其制造方法。半导体封装包括：印刷电路板（PCB）; 附着在PCB上的第一半导体芯片; 附接到所述第一半导体芯片以覆盖所述第一半导体芯片的一部分的插入器，并且包括分别在与所述第一半导体芯片的表面相对的上表面上彼此电连接的第一连接焊盘单元和第二连接焊盘单元内插器面向第一个半导体芯片; 安装在第一半导体芯片上的第二半导体芯片和作为倒装芯片型的插入器; 将所述插入件的所述第二连接垫单元与所述PCB或所述第一半导体芯片电连接到所述PCB的多个接合线; 以及形成在PCB上以围绕第一半导体芯片，第二半导体芯片，插入件和接合线的密封构件。

2. 发明授权

US06608380B2 Semiconductor chip package having one or more sealing screws 失效
标题翻译：具有一个或多个密封螺钉的半导体芯片封装
公开(公告)号：US06608380B2
公开(公告)日：2003-08-19
申请号：US09975470
申请日：2001-10-09
申请人： Young-Hoon Ro , Jung-Hwan Chun , Heung-Kyu Kwon
发明人： Young-Hoon Ro , Jung-Hwan Chun , Heung-Kyu Kwon
IPC分类号： H01L2334
CPC分类号： H01L23/4006 , H01L23/10 , H01L2023/405 , H01L2023/4087 , H01L2224/73253 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105
摘要： A semiconductor chip package comprising a chip with a lid having venting holes hermetically sealed with screws and a manufacturing method thereof are provided. The semiconductor chip package of the present invention comprises a chip such as a central processing unit (CPU) chip generating a large amount of heat; a substrate having upper and lower surfaces, the chip attached to the upper surface of the substrate; external connection terminals extending from the lower surface of the substrate and electrically connected to the chip; a lid attached to the upper surface of the substrate. The lid has a cavity for receiving the chip on a lower surface and venting holes penetrating the lid. The package includes sealing screws for hermetically sealing the venting holes. With the present invention, the venting holes formed through the lid are hermetically sealed without creating any voids or cracks in the sealant as in the prior art.
摘要翻译：提供一种半导体芯片封装，其包括具有盖子的芯片，所述盖子具有用螺钉密封的通气孔及其制造方法。本发明的半导体芯片封装包括产生大量热量的中央处理单元（CPU）芯片等芯片; 具有上表面和下表面的衬底，所述芯片附接到衬底的上表面; 外部连接端子从基板的下表面延伸并电连接到芯片; 附接到基板的上表面的盖。盖具有用于在下表面上接收芯片并且穿透穿透盖的通孔的空腔。该包装包括用于密封通风孔的密封螺钉。利用本发明，通过盖子形成的排气孔如现有技术那样气密地密封，而不产生密封剂中的任何空隙或裂缝。

3. 发明授权

US08202744B2 Wafer through silicon via forming method and equipment therefor 有权
标题翻译：通过其形成方法和设备通过硅晶片
公开(公告)号：US08202744B2
公开(公告)日：2012-06-19
申请号：US12512813
申请日：2009-07-30
申请人： Jung Hwan Chun , Gyu Han Kim
发明人： Jung Hwan Chun , Gyu Han Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76898
摘要： Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.
摘要翻译：提供了一种晶片通过硅通孔（TSV）的形成方法及其设备。晶片TSV形成方法包括布置具有其上形成有电路区域的正面的晶片的操作; 通过使用图像识别照相机识别晶片正面的电路区域中的接合焊盘的位置，并且将位置的识别转换为相对于晶片的背面的接合焊盘位置信息; 翻转晶片; 通过使用激光以通过使用来自图像识别照相机的接合焊盘位置信息来匹配接合焊盘的位置的方式在晶片的后表面中形成具有中间深度的蚀刻孔; 并且在其中形成有具有中间深度的蚀刻孔的背表面上进行等离子体各向同性蚀刻，从而形成贯穿接合焊盘的TSV。

4. 发明申请

US20100279511A1 Wafer Through Silicon Via Forming Method And Equipment Therefor 有权
标题翻译：通过硅片通过成型方法和设备来晶圆
公开(公告)号：US20100279511A1
公开(公告)日：2010-11-04
申请号：US12512813
申请日：2009-07-30
申请人： Jung Hwan CHUN , Gyu Han KIM
发明人： Jung Hwan CHUN , Gyu Han KIM
IPC分类号： H01L21/3065 , H01L21/306 , H01L21/465 , C23F1/08
CPC分类号： H01L21/76898
摘要： Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.
摘要翻译：提供了一种晶片通过硅通孔（TSV）的形成方法及其设备。晶片TSV形成方法包括布置具有其上形成有电路区域的正面的晶片的操作; 通过使用图像识别照相机识别晶片正面的电路区域中的接合焊盘的位置，并且将位置的识别转换为相对于晶片的背面的接合焊盘位置信息; 翻转晶片; 通过使用激光以通过使用来自图像识别照相机的接合焊盘位置信息来匹配接合焊盘的位置的方式在晶片的后表面中形成具有中间深度的蚀刻孔; 并且在其中形成有具有中间深度的蚀刻孔的背表面上进行等离子体各向同性蚀刻，从而形成贯穿接合焊盘的TSV。

5. 发明授权

US09024452B2 Semiconductor package comprising an interposer and method of manufacturing the same 有权
标题翻译：包括插入件的半导体封装及其制造方法
公开(公告)号：US09024452B2
公开(公告)日：2015-05-05
申请号：US13479971
申请日：2012-05-24
申请人： Jung Hwan Chun
发明人： Jung Hwan Chun
IPC分类号： H01L23/538 , H01L25/065 , H01L25/07 , H01L23/00 , H01L21/56 , H01L23/31 , H01L23/498
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/14 , H01L24/17 , H01L24/73 , H01L24/92 , H01L25/074 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92242 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06572 , H01L2924/01029 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/0665 , H01L2224/81
摘要： A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.
摘要翻译：半导体封装及其制造方法。半导体封装包括：印刷电路板（PCB）; 附着在PCB上的第一半导体芯片; 附接到所述第一半导体芯片以覆盖所述第一半导体芯片的一部分的插入器，并且包括分别在与所述第一半导体芯片的表面相对的上表面上彼此电连接的第一连接焊盘单元和第二连接焊盘单元内插器面向第一个半导体芯片; 安装在第一半导体芯片上的第二半导体芯片和作为倒装芯片型的插入器; 将所述插入件的所述第二连接垫单元与所述PCB或所述第一半导体芯片电连接到所述PCB的多个接合线; 以及形成在PCB上以围绕第一半导体芯片，第二半导体芯片，插入件和接合线的密封构件。

6. 发明申请

US20100311223A1 Method Of Dicing Wafer Using Plasma 有权
标题翻译：使用等离子体切割晶片的方法
公开(公告)号：US20100311223A1
公开(公告)日：2010-12-09
申请号：US12549825
申请日：2009-08-28
申请人： Jung Hwan Chun , Gyu Han Kim
发明人： Jung Hwan Chun , Gyu Han Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/78
摘要： Provided is a method of dicing a wafer that is thin and includes a low-K material using plasma without causing chipping and cracking during sawing without using an etch mask and without performing a separate wafer coating process. The method includes recognizing scribe lines of a front side of the wafer by using an image recognizing unit to obtain recognition information, performing two etching processes, wherein at least one includes plasma etching, on a backside of the wafer by using the recognition information to separate the wafer into a plurality of semiconductor chips, and adhering the plurality of semiconductor chips to an extended tape or a die attach film.
摘要翻译：提供了一种使用等离子体切割晶片的方法，其使用等离子体而不会在锯切期间造成切屑和裂纹，而不使用蚀刻掩模并且不执行单独的晶片涂布工艺，从而切割薄的晶片。该方法包括通过使用图像识别单元来识别晶片的正面的划线以获得识别信息，执行两个蚀刻处理，其中至少一个蚀刻工艺包括通过使用识别信息分离在晶片的背面上的等离子体蚀刻将晶片分成多个半导体芯片，并将多个半导体芯片粘合到扩展带或芯片附着膜。

7. 发明申请

US20130082405A1 Semiconductor Package 有权
标题翻译：半导体封装
公开(公告)号：US20130082405A1
公开(公告)日：2013-04-04
申请号：US13458397
申请日：2012-04-27
申请人： Jung Hwan Chun
发明人： Jung Hwan Chun
IPC分类号： H01L23/48
CPC分类号： H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/105 , H01L2224/05553 , H01L2224/32145 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/85005 , H01L2224/92247 , H01L2225/06562 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.
摘要翻译：一种半导体封装，包括具有第一半导体芯片的第一封装，与第一半导体芯片电连接的多个第一内部引线以及从第一内部引线延伸并电连接到外部装置的多个第一外部引线; 以及第二封装，具有第二半导体芯片和与第二半导体芯片电连接的多个第二内部引线，其中第一半导体芯片的非工作表面和第二半导体芯片的非活性表面彼此面对，第一内部引线接触第二内引线彼此电连接。

8. 发明授权

US08952514B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08952514B2
公开(公告)日：2015-02-10
申请号：US13458397
申请日：2012-04-27
申请人： Jung Hwan Chun
发明人： Jung Hwan Chun
IPC分类号： H01L23/02 , H01L23/495 , H01L25/10 , H01L23/00
CPC分类号： H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/105 , H01L2224/05553 , H01L2224/32145 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/85005 , H01L2224/92247 , H01L2225/06562 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.
摘要翻译：一种半导体封装，包括具有第一半导体芯片的第一封装，与第一半导体芯片电连接的多个第一内部引线以及从第一内部引线延伸并电连接到外部装置的多个第一外部引线; 以及第二封装，具有第二半导体芯片和与第二半导体芯片电连接的多个第二内部引线，其中第一半导体芯片的非工作表面和第二半导体芯片的非活性表面彼此面对，第一内部引线接触第二内引线彼此电连接。

9. 发明授权

US08222120B2 Method of dicing wafer using plasma 有权
标题翻译：使用等离子体切片晶片的方法
公开(公告)号：US08222120B2
公开(公告)日：2012-07-17
申请号：US12549825
申请日：2009-08-28
申请人： Jung Hwan Chun , Gyu Han Kim
发明人： Jung Hwan Chun , Gyu Han Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/78
摘要： Provided is a method of dicing a wafer that is thin and includes a low-K material using plasma without causing chipping and cracking during sawing without using an etch mask and without performing a separate wafer coating process. The method includes recognizing scribe lines of a front side of the wafer by using an image recognizing unit to obtain recognition information, performing two etching processes, wherein at least one includes plasma etching, on a backside of the wafer by using the recognition information to separate the wafer into a plurality of semiconductor chips, and adhering the plurality of semiconductor chips to an extended tape or a die attach film.
摘要翻译：提供了一种使用等离子体切割晶片的方法，其使用等离子体而不会在锯切期间造成切屑和裂纹，而不使用蚀刻掩模并且不执行单独的晶片涂布工艺，从而切割薄的晶片。该方法包括通过使用图像识别单元来识别晶片的正面的划线以获得识别信息，执行两个蚀刻处理，其中至少一个蚀刻工艺包括通过使用识别信息分离在晶片的背面上的等离子体蚀刻将晶片分成多个半导体芯片，并将多个半导体芯片粘合到扩展带或芯片附着膜。

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