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1. 发明授权

US07656678B2 Stacked module systems 有权
标题翻译：堆叠模块系统
公开(公告)号：US07656678B2
公开(公告)日：2010-02-02
申请号：US11263627
申请日：2005-10-31
申请人： Julian Partridge , James Douglas Wehrly, Jr. , David L. Roper , Joseph Villani
发明人： Julian Partridge , James Douglas Wehrly, Jr. , David L. Roper , Joseph Villani
IPC分类号： H05K7/10 , H05K7/12
CPC分类号： H01L23/49833 , H01L23/5385 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73253 , H01L2225/06517 , H01L2225/06579 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H05K3/305 , H05K2201/056 , H05K2201/10734 , Y02P70/613 , H01L2224/0401
摘要： The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to additional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.
摘要翻译：本发明将集成电路封装堆叠成电路模块。在优选实施例中，焊膏和主粘合剂分别施加到柔性电路上的选定位置。补充粘合剂应用于柔性电路，CSP或其他部件上的附加位置。柔性电路和CSP彼此接近。在回流焊接操作期间，施加力并且CSP朝向柔性电路折叠，使主粘合剂和补充粘合剂移位。补充粘合剂建立了粘合，为柔性电路提供额外的支撑。在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此结合或连接到其它部件。快速粘合粘合剂在组装期间保持粘合的包装和/或部件的对准，并且结构粘合粘合剂为粘合剂提供附加的强度和/或结构完整性。

2. 发明申请

US20080308924A1 Circuit Module Having Force Resistant Construction 有权
标题翻译：具有抗电阻结构的电路模块
公开(公告)号：US20080308924A1
公开(公告)日：2008-12-18
申请号：US12197674
申请日：2008-08-25
申请人： Leland Szewerenko , Julian Partridge , Ron Orris
发明人： Leland Szewerenko , Julian Partridge , Ron Orris
IPC分类号： H01L23/48 , G06K9/00
CPC分类号： H01L23/4985 , H01L23/3128 , H01L23/3135 , H01L23/315 , H01L2924/0002 , H01L2924/00
摘要： Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
摘要翻译：公开了用于封装具有传感器区域的模具的抗冲击电路模块。优选的模块包括柔性电路和与其耦合的管芯。柔性电路优选地折叠在可压缩材料上以帮助吸收施加的力。可以在模具的侧面和可压缩材料之间提供间隙以帮助防止剥离。金属加强层可以结合到模具的背面。可以使用包括在模具下面的图案化间隙的低模量材料来吸收力。可以将干膜粘合剂放置在模具的上表面的至少一部分和柔性电路之间，优选地提供进一步的点冲击强度和保护。高和低模量材料可以结合在加固结构中。还教授了采用这种电路模块的消费者设备，以及模块构造方法。

3. 发明申请

US20080122054A1 Circuit Module Having Force Resistant Construction 有权
标题翻译：具有抗电阻结构的电路模块
公开(公告)号：US20080122054A1
公开(公告)日：2008-05-29
申请号：US11556124
申请日：2006-11-02
申请人： Leland Szewerenko , Julian Partridge , Ron Orris
发明人： Leland Szewerenko , Julian Partridge , Ron Orris
IPC分类号： H01L29/84
CPC分类号： H01L23/4985 , H01L23/3128 , H01L23/3135 , H01L23/315 , H01L2924/0002 , H01L2924/00
摘要： Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
摘要翻译：公开了用于封装具有传感器区域的模具的抗冲击电路模块。优选的模块包括柔性电路和与其耦合的管芯。柔性电路优选地折叠在可压缩材料上以帮助吸收施加的力。可以在模具的侧面和可压缩材料之间提供间隙以帮助防止剥离金属增强层可以结合到模具的背面。可以使用包括在模具下面的图案化间隙的低模量材料来吸收力。可以将干膜粘合剂放置在模具的上表面的至少一部分和柔性电路之间，优选地提供进一步的点冲击强度和保护。高和低模量材料可以结合在加固结构中。还教授了采用这种电路模块的消费者设备，以及模块构造方法。

4. 发明申请

US20070290313A1 Interposer stacking system and method 有权
标题翻译：内插堆叠系统和方法
公开(公告)号：US20070290313A1
公开(公告)日：2007-12-20
申请号：US11452532
申请日：2006-06-14
申请人： Julian Partridge
发明人： Julian Partridge
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K1/141 , H05K2201/049 , H05K2201/10378 , H05K2201/10515 , H05K2201/10689 , H01L2924/00
摘要： The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.
摘要翻译：本发明提供了一种系统和方法，用于选择性地堆叠和互连带有封装的集成电路器件，其上部IC元件的引线的脚与下部IC元件的引线的上部肩部之间的连接，组成IC之间的堆叠连接在沿着堆叠的引导侧定向的插入件或载体结构中实现，并且延伸超过构成IC的引线的脚的周边或超过插入器的连接焊盘。这使得空气流动，下部引线的大部分转接段用于冷却，但是提供了一种不太复杂的板结构，用于实现堆叠内连接。

5. 发明授权

US07094632B2 Low profile chip scale stacking system and method 有权
标题翻译：薄型芯片级堆叠系统及方法
公开(公告)号：US07094632B2
公开(公告)日：2006-08-22
申请号：US10873847
申请日：2004-06-22
申请人： James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
发明人： James W. Cady , Julian Partridge , James Douglas Wehrly, Jr. , James Wilder , David L. Roper , Jeff Buchle
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2224/81801 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , Y10T29/49126 , Y10T29/49144
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。该柔性电路可以表现出一个或两个或更多个导电层。在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如，柔性电路作为热转移材料。

6. 发明授权

US07804985B2 Circuit module having force resistant construction 有权
标题翻译：电路模块具有抗压结构
公开(公告)号：US07804985B2
公开(公告)日：2010-09-28
申请号：US12197674
申请日：2008-08-25
申请人： Leland Szewerenko , Julian Partridge , Ron Orris
发明人： Leland Szewerenko , Julian Partridge , Ron Orris
IPC分类号： H01L31/00
CPC分类号： H01L23/4985 , H01L23/3128 , H01L23/3135 , H01L23/315 , H01L2924/0002 , H01L2924/00
摘要： Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
摘要翻译：公开了用于封装具有传感器区域的模具的抗冲击电路模块。优选的模块包括柔性电路和与其耦合的管芯。柔性电路优选地折叠在可压缩材料上以帮助吸收施加的力。可以在模具的侧面和可压缩材料之间提供间隙以帮助防止剥离。金属加强层可以结合到模具的背面。可以使用包括在模具下面的图案化间隙的低模量材料来吸收力。可以将干膜粘合剂放置在模具的上表面的至少一部分和柔性电路之间，优选地提供进一步的点冲击强度和保护。高和低模量材料可以结合在加固结构中。还教授了采用这种电路模块的消费者设备，以及模块构造方法。

7. 发明授权

US07675155B2 Carrier structure stacking system and method 有权
标题翻译：载体结构堆垛系统及方法
公开(公告)号：US07675155B2
公开(公告)日：2010-03-09
申请号：US12262927
申请日：2008-10-31
申请人： Julian Partridge
发明人： Julian Partridge
IPC分类号： H01L23/02
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K3/429 , H05K2201/09481 , H05K2201/0959 , H05K2201/10515 , H05K2201/10689 , H05K2201/2018 , H01L2924/00
摘要： The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.
摘要翻译：本发明提供了一种系统和方法，用于选择性地堆叠和互连带引线的封装集成电路器件，其具有上IC的引线的脚与下IC的引线的上肩之间的连接，而实现堆叠相关的堆叠内的导电性转换组成IC之间的连接在沿着堆叠的引导侧定向的多层插入件或载体结构中实现，其中选定的导电转移与其它选定的导电转换电互连。

8. 发明申请

US20090294948A1 Contrast Interposer Stacking System And Method 审中-公开
标题翻译：对比度内插系统和方法
公开(公告)号：US20090294948A1
公开(公告)日：2009-12-03
申请号：US12538757
申请日：2009-08-10
申请人： Julian Partridge , Roel Perez , Leland Szewerenko
发明人： Julian Partridge , Roel Perez , Leland Szewerenko
IPC分类号： H01L23/02 , H01L23/495
CPC分类号： H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K1/141 , H05K2201/049 , H05K2201/10378 , H05K2201/10515 , H05K2201/10689 , H01L2924/00
摘要： The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
摘要翻译：本描述提供了在堆叠实施例中的插入器和引线之间的增加的对比度，其采用延伸超过由组成IC器件的引线建立的边界或周边的插入器。

9. 发明申请

US20090072376A1 Carrier Structure Stacking System and Method 有权
标题翻译：载体结构堆叠系统及方法
公开(公告)号：US20090072376A1
公开(公告)日：2009-03-19
申请号：US12262927
申请日：2008-10-31
申请人： Julian Partridge
发明人： Julian Partridge
IPC分类号： H01L23/48 , H01R12/14
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K3/429 , H05K2201/09481 , H05K2201/0959 , H05K2201/10515 , H05K2201/10689 , H05K2201/2018 , H01L2924/00
摘要： The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.
摘要翻译：本发明提供了一种系统和方法，用于选择性地堆叠和互连带引线的封装集成电路器件，其具有上IC的引线的脚与下IC的引线的上肩之间的连接，而实现堆叠相关的堆叠内的导电性转换组成IC之间的连接在沿着堆叠的引导侧定向的多层插入件或载体结构中实现，其中选定的导电转移与其它选定的导电转换电互连。

10. 发明授权

US07304382B2 Managed memory component 有权
公开(公告)号：US07304382B2
公开(公告)日：2007-12-04
申请号：US11436957
申请日：2006-05-18
申请人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
发明人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
IPC分类号： H01L23/34
CPC分类号： H01L23/13 , H01L23/5385 , H01L23/5387 , H01L25/18 , H01L2224/49175 , H01L2924/15311 , H05K1/147 , H05K1/182 , H05K1/189 , H05K3/326 , H05K2201/056 , H05K2201/091 , H05K2201/10515 , H05K2201/10689
摘要： The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

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