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1. 发明授权

US4709394A Multiplexed real-time pyramid signal processing system 失效
标题翻译：多路复用实时金字塔信号处理系统
公开(公告)号：US4709394A
公开(公告)日：1987-11-24
申请号：US768809
申请日：1985-08-23
申请人： Roger F. Bessler , James H. Arbeiter , Joseph O. Sinniger
发明人： Roger F. Bessler , James H. Arbeiter , Joseph O. Sinniger
IPC分类号： H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54
CPC分类号： G06F17/10 , H04N19/63 , H04N7/54 , H04N19/42
摘要： The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
摘要翻译：执行代表n维信息分量或（如视频信号）的采样时间信号的Burt Pyramid或FSD（滤除 - 减去 - 抽取）金字塔分析器（或合成器）级所需的硬件量大大减少通过采用时间同步复用分析器级来导出以预定的时间顺序格式排列的预定多个子频谱的单个串行串流样本的（或时间同步复用合成器级）根据给定的一组时间同步，重复产生，串行施加的控制信号彼此相对。

2. 发明授权

US4375209A Digital timing system for spark advance 失效
标题翻译：数字定时系统，用于火花提前
公开(公告)号：US4375209A
公开(公告)日：1983-03-01
申请号：US161454
申请日：1980-06-20
申请人： Joseph O. Sinniger , Anthony D. Robbi
发明人： Joseph O. Sinniger , Anthony D. Robbi
IPC分类号： F02P5/15 , G05B15/02 , H03K5/26 , F02P5/04
CPC分类号： F02P5/1514 , Y02T10/46
摘要： A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.
摘要翻译：根据发动机速度设置火花正时的方法包括计数发动机转速参考脉冲之间的计数时钟脉冲。只读存储器具有连续的存储位置，每个存储位置存储加数和重复数。包括累加器的加法器单元操作以访问存储器位置，并且将加数量反复添加到累加器的内容中等于各个重复次数的次数。当累加器的内容与计数器提供的参考周期数相对应时，比较器产生点火点火脉冲。

3. 发明授权

US4538262A Multiplex bus system for controlling the transmission of data between a master control unit and a plurality of remotely located receiver-transmitter units 失效
标题翻译：用于控制主控制单元与多个远程定位的接收机 - 发射机单元之间的数据传输的多路总线系统
公开(公告)号：US4538262A
公开(公告)日：1985-08-27
申请号：US520122
申请日：1983-08-03
申请人： Joseph O. Sinniger , Richard M. Peterson
发明人： Joseph O. Sinniger , Richard M. Peterson
IPC分类号： B60R16/02 , B60R16/03 , H04L7/06 , H04L12/40 , H04Q9/14 , H04J3/06 , H04J3/02
CPC分类号： H04L12/403 , H04L12/40 , H04Q9/14 , B60R16/0315 , H04L2012/40273 , H04L7/06
摘要： A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
摘要翻译：多路复用总线系统包括通过数据总线连接到至少一个接收机发送单元（RTU）的主控单元（MCU）。 MCU向RTU发送包括已知持续时间的同步脉冲和连续的时间间隔定时信号的消息，该时间间隔T标记要从RTU发送到MCU的数据位的边界。 RTU包括时钟脉冲源，其利用同步脉冲以每个持续时间T以P个脉冲确定时钟脉冲源的频率。值P与定时信号结合使用以在数据位中产生适当定时的数据确定信号。

4. 发明授权

US4408296A Digital timing system for spark advance 失效
标题翻译：数字定时系统，用于火花提前
公开(公告)号：US4408296A
公开(公告)日：1983-10-04
申请号：US181941
申请日：1980-08-27
申请人： Anthony D. Robbi , Joseph O. Sinniger
发明人： Anthony D. Robbi , Joseph O. Sinniger
IPC分类号： F02P5/15 , F02P5/14 , G06M3/02
CPC分类号： F02P5/1514 , G06Q30/0283 , Y02T10/46
摘要： A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter. Improved memory addressing means facilitates altering the spark advance in accordance with a sensed condition such as manifold vacuum, and conserves memory space.
摘要翻译：根据发动机速度设置火花正时的方法包括计数发动机转速参考脉冲之间的计数时钟脉冲。只读存储器具有存储加数和重复数的连续存储单元。包括累加器的加法器单元操作以访问存储器位置，并且将加数量反复添加到累加器的内容中等于各个重复次数的次数。当累加器的内容与计数器提供的参考周期数相对应时，比较器产生点火点火脉冲。改进的存储器寻址装置有助于根据诸如歧管真空的感测条件来改变火花提前，并且节省存储空间。

5. 发明授权

US5276513A Implementation architecture for performing hierarchical motion analysis of video images in real time 失效
标题翻译：用于实时地执行视频图像的分层运动分析的实现架构
公开(公告)号：US5276513A
公开(公告)日：1994-01-04
申请号：US896771
申请日：1992-06-10
申请人： Gooitzen S. van der Wal , Joseph O. Sinniger , Charles H. Anderson
发明人： Gooitzen S. van der Wal , Joseph O. Sinniger , Charles H. Anderson
IPC分类号： G06F12/00 , G06F12/08 , G06T7/20 , H04N5/14 , H04N7/26 , H04N7/32 , H04N7/137
CPC分类号： H04N5/145 , G06T7/2073 , H04N19/53 , H04N19/537
摘要： First circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real time, with minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.
摘要翻译：包括给定数量的现有技术的图像 - 金字塔阶段的第一电路装置与包括相同给定数量的新的运动矢量级的第二电路装置一起实时执行成本有效的分层运动分析（HMA），具有最小系统处理延迟和/或采用最小硬件结构。具体地说，第一和第二电路装置响应于以比较高的帧速率（例如，30帧每秒）发生的连续的给定像素密度图像数据帧的正在进行的输入序列的相对较高分辨率的图像数据，在一定的处理系统延迟之后，导出以相同给定帧速率发生的连续给定像素密度矢量数据帧的持续输出序列。每个矢量数据帧指示在每对连续图像帧之间发生的图像运动。

6. 发明授权

US4638498A Digital timing system 失效
标题翻译：数字定时系统
公开(公告)号：US4638498A
公开(公告)日：1987-01-20
申请号：US780898
申请日：1985-09-27
申请人： Joseph O. Sinniger , Anthony D. Robbi
发明人： Joseph O. Sinniger , Anthony D. Robbi
IPC分类号： F02P5/15 , G06M3/02 , F02P5/04
CPC分类号： F02P5/1514 , Y02T10/46
摘要： A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.
摘要翻译：根据发动机速度设置火花正时的方法包括计数发动机转速参考脉冲之间的计数时钟脉冲。只读存储器具有连续的存储位置，每个存储位置存储加数和重复数。包括累加器的加法器单元操作以访问存储器位置，并且将加数量反复添加到累加器的内容中等于各个重复次数的次数。当累加器的内容与计数器提供的参考周期数相对应时，比较器产生点火点火脉冲。

7. 发明授权

US4575809A Digital timing method for spark advance 失效
标题翻译：数字定时方法用于火花提前
公开(公告)号：US4575809A
公开(公告)日：1986-03-11
申请号：US437836
申请日：1982-10-29
申请人： Joseph O. Sinniger , Anthony D. Robbi
发明人： Joseph O. Sinniger , Anthony D. Robbi
IPC分类号： F02P5/15 , F02P5/04
CPC分类号： F02P5/1514 , Y02T10/46
摘要： A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.
摘要翻译：根据发动机速度设置火花正时的方法包括计数发动机转速参考脉冲之间的计数时钟脉冲。只读存储器具有连续的存储位置，每个存储位置存储加数和重复数。包括累加器的加法器单元操作以访问存储器位置，并且将加数量反复添加到累加器的内容中等于各个重复次数的次数。当累加器的内容与计数器提供的参考周期数相对应时，比较器产生点火点火脉冲。

8. 发明授权

US4365202A Duty cycle generator with improved resolution 失效
标题翻译：占空比发生器，分辨率提高
公开(公告)号：US4365202A
公开(公告)日：1982-12-21
申请号：US180903
申请日：1980-08-25
申请人： Joseph O. Sinniger
发明人： Joseph O. Sinniger
IPC分类号： F02B1/04 , F02D41/24 , H03K3/017 , H03K7/08 , H03K5/05
CPC分类号： H03K3/017 , F02D41/2403 , H03K7/08 , F02B1/04
摘要： A digitized duty cycle pulse generator capable of resolution finer than the period of the available source clock signal. The invention comprises a means for generating a clock pulse signal having a repetition of f.sub.c, counter means responsive to said clock pulse signal to cycle iteratively through a count of n, and storage means for storing a variable binary value m, where m m during first selected cycles of said counter means through said count of n, and to produce said first logic level signal when l (m+1) and during second selected cycles of said counter means through said count of n.
摘要翻译：数字化占空比脉冲发生器能够比可用源时钟信号的周期更精细。本发明包括用于产生具有重复fc的时钟脉冲信号的装置，响应于所述时钟脉冲信号的计数装置迭代地循环计数n，以及用于存储可变二进制值m的存储装置，其中m m，并且当l>（m + 1）时产生所述第一逻辑电平信号，并且在l>（m + 1）时产生所述第一逻辑电平信号，并且在第二所述计数器装置的选定循环通过所述计数n。

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