专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06741108B1 Method and circuit to reduce jitter generation in a PLL using a reference quadrupler and an equalizer 有权
标题翻译：使用参考四通道和均衡器来减少PLL中抖动产生的方法和电路
公开(公告)号：US06741108B1
公开(公告)日：2004-05-25
申请号：US10132462
申请日：2002-04-25
申请人： Joseph James Balardeta , Allen Carl Merrill , Wei Fu
发明人： Joseph James Balardeta , Allen Carl Merrill , Wei Fu
IPC分类号： H03L706
CPC分类号： H03L7/18 , H03L2207/10 , Y10S331/02
摘要： A method of reducing jitter in a phase locked loop (PLL) includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and providing the second reference signal to a frequency phase detector of the PLL. The method may also include equalizing the second reference signal prior to providing the second reference signal to the frequency phase detector. The method can be accomplished by a circuit, wherein quadrupling the frequency of the first reference signal is performed by two frequency doublers arranged in series. The step of equalizing can be performed by two equalizers, each one configured to equalize an output of a respective frequency doubler.
摘要翻译：减少锁相环（PLL）抖动的方法包括：接收第一参考信号，将第一参考信号的频率加倍四倍以产生第二参考信号，以及将第二参考信号提供给PLL的频率相位检测器。该方法还可以包括在将第二参考信号提供给频率相位检测器之前均衡第二参考信号。该方法可以由电路完成，其中通过串联布置的两个倍频器来执行第四参考信号的频率的四倍。均衡步骤可以由两个均衡器执行，每个均衡器被配置为均衡相应倍频器的输出。

2. 发明授权

US06657464B1 Method and circuit to reduce jitter generation in a PLL using a reference quadrupler, equalizer, and phase detector with control for multiple frequencies 有权
标题翻译：使用参考四通道，均衡器和具有多个频率控制的相位检测器来减少PLL中抖动产生的方法和电路
公开(公告)号：US06657464B1
公开(公告)日：2003-12-02
申请号：US10132425
申请日：2002-04-25
申请人： Joseph James Balardeta , Allen Carl Merrill , Wei Fu
发明人： Joseph James Balardeta , Allen Carl Merrill , Wei Fu
IPC分类号： H03L706
CPC分类号： H03L7/18 , H03L7/087 , H03L7/091 , H03L7/113 , Y10S331/02
摘要： A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal. The PLL further includes a multiplexer configured for initially receiving the first error signal until the frequencies of the first divided VCO output signal feedback signal and the second reference signal match, and thereafter for receiving the second error signal, and to provide the first or second error signal to the filter.
摘要翻译：低抖动锁相环（PLL）电路包括参考信号发生器和PLL。参考信号发生器被配置为将第一参考信号的频率加倍以产生第二参考信号。 PLL包括与压控振荡器（VCO）串联耦合的滤波器，以及频率相位检测器，被配置为基于第二参考信号和第一分频VCO输出信号之间的频率差产生第一误差信号。 PLL还包括相位检测器，其被配置为在第二参考信号的每个上升和下降转换时基于第二参考信号和第二分频VCO输出信号之间的相位差产生第二误差信号。 PLL还包括被配置为初始接收第一误差信号的多路复用器，直到第一分频VCO输出信号反馈信号和第二参考信号的频率匹配，然后用于接收第二误差信号，并且提供第一或第二误差信号到过滤器。

3. 发明授权

US07254173B1 Digitally adjusted high speed analog equalizer 有权
标题翻译：数字调节高速模拟均衡器
公开(公告)号：US07254173B1
公开(公告)日：2007-08-07
申请号：US10394844
申请日：2003-03-21
申请人： Wei Fu , Joseph James Balardeta
发明人： Wei Fu , Joseph James Balardeta
IPC分类号： H03H7/40
CPC分类号： H04L25/0272 , H04L25/0292
摘要： A high speed CMOS-implemented equalizer architecture as described herein utilizes a digitally controlled analog equalization scheme to equalize intersymbol interference present in an input signal. The equalizer structure includes an inductor high frequency gain boosting stage and a feed forward high frequency equalizer stage connected in series. The equalization performed by each of these gain boosting stages is controlled by one or more digital control signals. The combination of these stages results in the equalization of both amplitude and phase distortion. The equalizer architecture is suitable for use with communication systems that operate at 11.2 Gbps speeds.
摘要翻译：如本文所述的高速CMOS实现的均衡器架构利用数字控制的模拟均衡方案来均衡输入信号中存在的符号间干扰。均衡器结构包括串联连接的电感器高频增益增益级和前馈高频均衡器级。由这些增益级中的每一个执行的均衡由一个或多个数字控制信号控制。这些级的组合导致幅度和相位失真的均衡。均衡器架构适用于以11.2 Gbps速度工作的通信系统。

4. 发明授权

US07132861B1 Amplifier with digital DC offset cancellation feature 有权
标题翻译：具有数字直流偏移消除功能的放大器
公开(公告)号：US07132861B1
公开(公告)日：2006-11-07
申请号：US11134867
申请日：2005-05-20
申请人： Wei Fu , Joseph James Balardeta
发明人： Wei Fu , Joseph James Balardeta
IPC分类号： H03F3/45
CPC分类号： H03F3/45968 , H03F3/45744 , H03F2203/45366 , H03F2203/45544 , H03F2203/45598
摘要： A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.
摘要翻译：如本文所述的高速，高灵敏度后置放大器包括数字控制的DC偏移消除特征。放大器电路被配置为响应于数字控制信号提供DC偏移电压电平，其中基于诸如误码率的数据误差度量而产生数字控制信号。放大器电路中的交流信号路径和直流偏移调整信号路径被分离以便于以正常的电源电压进行操作，并实现低功率操作。

5. 发明授权

US06897700B1 Amplifier with digital DC offset cancellation feature 有权
标题翻译：具有数字直流偏移消除功能的放大器
公开(公告)号：US06897700B1
公开(公告)日：2005-05-24
申请号：US10394845
申请日：2003-03-21
申请人： Wei Fu , Joseph James Balardeta
发明人： Wei Fu , Joseph James Balardeta
IPC分类号： H03F3/45 , H03L5/00
CPC分类号： H03F3/45968 , H03F3/45744 , H03F2203/45366 , H03F2203/45544 , H03F2203/45598
摘要： A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.
摘要翻译：如本文所述的高速，高灵敏度后置放大器包括数字控制的DC偏移消除特征。放大器电路被配置为响应于数字控制信号提供DC偏移电压电平，其中基于诸如误码率的数据误差度量而产生数字控制信号。放大器电路中的交流信号路径和直流偏移调整信号路径被分离以便于以正常的电源电压进行操作，并实现低功率操作。

6. 发明授权

US06538520B1 Methods and apparatus for producing a reference frequency signal with use of a reference frequency quadrupler having frequency selection controls 有权
标题翻译：使用具有频率选择控制的参考频率四倍频器来产生参考频率信号的方法和装置
公开(公告)号：US06538520B1
公开(公告)日：2003-03-25
申请号：US09982156
申请日：2001-10-18
申请人： Allen Carl Merrill , Joseph James Balardeta , Wei Fu , Mehmet Eker
发明人： Allen Carl Merrill , Joseph James Balardeta , Wei Fu , Mehmet Eker
IPC分类号： H03B1900
CPC分类号： H03K5/00006 , G06F7/68 , H03B19/14 , H03L7/18 , H03L2207/10
摘要： Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.
摘要翻译：锁相环（PLL）的电路包括第一倍频器; 第一均衡器，具有耦合到第一倍频器的输出的输入; 第二倍频器，具有耦合到所述第一均衡器的输出的输入; 以及第二均衡器，其具有耦合到第二倍频器的输出的输入和馈送到PLL的输出。每个倍频器包括具有耦合到倍频器的输入的输入的第一延迟电路; 以及具有耦合到延迟电路的输出的第一输入和耦合到倍频器的输入的第二输入的XOR电路。两个频率倍增器的组合将参考信号串联四倍于PLL，这允许PLL具有较小的反馈分频比和较高的环路增益，以减少抖动。有利地，提供了用于选择初始参考信号的控制。

7. 发明授权

US06720806B1 Method and circuit for producing a reference frequency signal using a reference frequency doubler having frequency selection controls 有权
标题翻译：使用具有频率选择控制的参考倍频器产生参考频率信号的方法和电路
公开(公告)号：US06720806B1
公开(公告)日：2004-04-13
申请号：US10132463
申请日：2002-04-25
申请人： Allen Carl Merrill , Joseph James Balardeta , Sudhaker Reddy Anumula
发明人： Allen Carl Merrill , Joseph James Balardeta , Sudhaker Reddy Anumula
IPC分类号： H03B1900
CPC分类号： H03L7/18 , H03K5/00006 , H03L2207/10
摘要： Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. The frequency doubler is provided with selection control for programming multiple frequencies.
摘要翻译：锁相环（PLL）的电路包括参考信号输入和倍频器。倍频器的输出是具有大约是初始参考信号的两倍的频率并被馈送到PLL的第二参考信号。倍频器包括具有耦合到倍频器的输入的输入的第一延迟电路; 以及具有耦合到延迟电路的输出的第一输入和耦合到倍频器的输入的第二输入的XOR电路。倍频器可以包括在第一延迟电路之后串联的一个或多个附加延迟电路，其输出被提供给多路复用器。多路复用器包括选择信号输入，用于选择要提供给异或电路的至少一个延迟电路的输出。倍频器允许PLL具有较小的反馈分频比和较高的环路增益，以减少抖动。倍频器具有用于编程多个频率的选择控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式