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1. 发明授权

US06529570B1 Data synchronizer for a multiple rate clock source and method thereof 有权
标题翻译：多速率时钟源的数据同步器及其方法
公开(公告)号：US06529570B1
公开(公告)日：2003-03-04
申请号：US09409768
申请日：1999-09-30
申请人： Steven C. Miller , Michael B. Galles , David M. Parry , Jon C. Gibbons
发明人： Steven C. Miller , Michael B. Galles , David M. Parry , Jon C. Gibbons
IPC分类号： H04L700
CPC分类号： H04L7/02
摘要： A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a receive data valid signal (48) by a signal generator (108) in response to a slow clock rate for the receive core clock (52). The second latch unit (96) generates a delayed select signal (B) that is used by the signal generator (108) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal (48) in response to a fast clock rate for the receive core clock (52).
摘要翻译：数据同步器（60）在选择器（82）处接收数据就绪信号（40）。响应于根据接收核心时钟（52）的时钟速度确定的速度选择信号（88），选择器（82）选择数据就绪信号（40）或数据就绪信号（40）的延迟版本，。选择器（82）向第一锁存单元（94）和第二锁存单元（96）提供选择信号（92）。第一锁存单元（94）响应于接收核心时钟（52）的慢时钟速率产生由信号发生器（108）作为接收数据有效信号（48）提供的锁存选择信号（A）。第二锁存单元（96）在提供接收数据有效信号（48）之前产生延迟选择信号（B），该延迟选择信号由信号发生器（108）用来去除插入锁存选择信号（A）中的额外宽度，响应于所述接收核心时钟（52）的快速时钟速率。

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