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    • 8. 发明授权
    • Method for reducing data storage and transmission requirements for
seismic data
    • 减少地震数据存储和传输要求的方法
    • US5745392A
    • 1998-04-28
    • US539415
    • 1995-10-05
    • Raymond A. ErgasPaul L. DonohoJohn Villasenor
    • Raymond A. ErgasPaul L. DonohoJohn Villasenor
    • G01V1/22G06T9/00G06F7/00
    • G01V1/22G06T9/005
    • A method for compressing seismic data to reduce data storage and transmission requirements applies wavelet transforms to digitized trace sequential data obtained from plural arrays of multiple acoustic sensors. The wavelet transforms are applied in at least three dimensions, and, in the case of underwater exploration, four dimensions. The transformed data is ordered and quantized to increase the number of zero data values, and the quantized data is compressed using rim-length encoding and entropy coding. The entropy coded data is stored for later retrieval or transmitted to a remote location. The retrieved or received data is decompressed, dequantized and inverse wavelet transformed to construct a representation of the original data. The compression can be selected to be in excess of 100:1 to significantly reduce the data storage and transmission requirements without significant degradation of the reconstructed data.
    • 一种用于压缩地震数据以减少数据存储和传输要求的方法将小波变换应用于从多个声学传感器的多个阵列获得的数字化跟踪顺序数据。 小波变换应用至少三维,在水下探测的情况下,四维。 经变换的数据被排序和量化以增加零数据值的数量,并且使用边缘长度编码和熵编码来压缩量化的数据。 熵编码数据被存储以供稍后检索或发送到远程位置。 检索或接收的数据进行解压缩,逆量化和逆小波变换,以构建原始数据的表示。 压缩可以选择为超过100:1,以显着降低数据存储和传输要求,而不会显着降低重构数据。
    • 10. 发明申请
    • Memory architectures including non-volatile memory devices
    • 内存架构包括非易失性存储器件
    • US20060227605A1
    • 2006-10-12
    • US11325224
    • 2006-01-03
    • David ChoiJohn Villasenor
    • David ChoiJohn Villasenor
    • G11C14/00
    • G11C5/04G11C5/147G11C11/005
    • Architectures are described that can include integrated non-volatile memory modules. Integrated non-volatile memory modules are a form of memory that is integrated on a single chip and includes at least one volatile memory cell and at least one non-volatile memory device. Information can be loaded between the at least one memory cell and the at least one non-volatile memory device in coordination with the supply of power to the integrated non-volatile memory device. In many embodiments, the supply of power to the integrated non-volatile memory device and the loading of information between the volatile memory cells and non-volatile memory devices are controlled to conserve energy. One embodiment of the present invention includes processing circuitry connected to an integrated non-volatile memory module and a power supply connected to the processing circuitry and integrated non-volatile memory module. In addition, the integrated non-volatile memory module is integrated on a single chip and includes at least one volatile memory cell that is connected to at least one non-volatile memory device.
    • 描述了可以包括集成的非易失性存储器模块的体系结构。 集成非易失性存储器模块是集成在单个芯片上并包括至少一个易失性存储器单元和至少一个非易失性存储器件的存储器形式。 与集成的非易失性存储器件的电力供应协调,可以在至少一个存储器单元和至少一个非易失性存储器件之间加载信息。 在许多实施例中,控制向集成的非易失性存储器件的电力供应和易失性存储器单元与非易失性存储器件之间的信息加载以节省能量。 本发明的一个实施例包括连接到集成非易失性存储器模块的处理电路和连接到处理电路和集成的非易失性存储器模块的电源。 此外,集成的非易失性存储器模块集成在单个芯片上,并且包括连接到至少一个非易失性存储器件的至少一个易失性存储器单元。