专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5864167A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5864167A
公开(公告)日：1999-01-26
申请号：US8335
申请日：1998-01-16
申请人： John R. Cutter
发明人： John R. Cutter
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L29/861 , H01L23/58
CPC分类号： H01L29/402 , H01L29/0638 , H01L29/7802 , H01L29/7813 , H01L2924/0002
摘要： In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of operation of the device. A field plate structure (34, 34a, 34b, 34c) on an insulating layer (24) over the body portion (11) extends towards the outer periphery (14) to spread a depletion layer from the reverse-biased p-n junction (5) towards the outer periphery (14). The channel stopper (4) comprises concentrically doped stopper regions (41 to 44) with different doping concentrations and/or region widths and/or spacings, giving to the body portion (11) a non-uniform doping profile the doping of which, under the field plate structure (34, 34a, 34b, 34c), increases with distance (D) towards the outer periphery (14) to slow progressively the spread of the depletion layer under the field plate structure (34, 34a, 34b, 34c). This field plate structure (34, 34a, 34b, 34c) connected to the device region (15) and/or to a field region (35) can extend laterally over the whole of the body portion (11) between the device region (15) and a doped channel stopper region (41) in the vicinity of the outer periphery (14), and without the complication of any field plate connected to the channel stopper (4).
摘要翻译：在MOSFET或其它高压装置中，环形通道止动器（4）围绕主体部分（11）的外周（14）延伸，器件区域（15）形成在高反向下可操作的pn结（5）在设备的至少一种操作模式中偏置。在主体部分（11）上的绝缘层（24）上的场板结构（34,34a，34b，34c）朝向外周边（14）延伸以从反向偏置的pn结（5）扩散耗尽层，朝向外周（14）。通道阻挡器（4）包括具有不同掺杂浓度和/或区域宽度和/或间隔的同心掺杂的停止区域（41至44），给体部分（11）提供不均匀的掺杂分布，其掺杂在下面场板结构（34,34a，34b，34c）随着朝向外周（14）的距离（D）而增加，以逐渐减小场板结构（34,34a，34b，34c）下的耗尽层的扩展，。连接到设备区域（15）和/或场区域（35）的该场板结构（34,34a，34b，34c）可以横跨整个主体部分（11）延伸到设备区域（15））和在外周（14）附近的掺杂沟道停止区域（41），并且没有与通道阻挡件（4）连接的任何场板的复杂性。

2. 发明授权

US07843259B2 Field effect transistor circuit and method of operation of field effect transistor circuit for reducing thermal runaway 有权
标题翻译：场效应晶体管电路和场效应晶体管电路的运行方法，用于减少热失控
公开(公告)号：US07843259B2
公开(公告)日：2010-11-30
申请号：US11658224
申请日：2005-07-18
申请人： John R. Cutter
发明人： John R. Cutter
IPC分类号： H01L25/00
CPC分类号： H01L29/7802 , H01L27/0251 , H01L29/41766 , H01L29/4238 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.
摘要翻译：场晶体管被分成多个单元（6），并且包括连接到第一晶体管单元（8）的单独的第一栅极线（20）和连接到第二晶体管单元（10）的单独的第二栅极线（22）。驱动电路用于在正常饱和操作状态下驱动所有单元（6），但是在线性操作状态仅驱动第二单元（10）以减少在线性操作状态中使用的单元数量。

3. 发明授权

US07443648B2 Driver for inductive load 有权
标题翻译：驱动器用于感性负载
公开(公告)号：US07443648B2
公开(公告)日：2008-10-28
申请号：US10552904
申请日：2004-04-08
申请人： John R. Cutter , Brendan P. Kelly
发明人： John R. Cutter , Brendan P. Kelly
IPC分类号： H01H47/00 , H01H9/00
CPC分类号： H03K17/6874 , H02M3/158 , H02M2003/1555 , H03K17/08142
摘要： A driver for an inductive load such as a solenoid coil 92 includes three FETs 4,6,8. Two of the FETs are reversely connected between battery and output terminals 16, 18, and one of the FETs is connected between output and ground terminals 16, 14. A driver circuit 10 having high and low side control circuitry 58,56 is formed in a common substrate with two of the FETs 4,6. In use, a coil 92 is connected to the output terminal 16, and driven in an energize mode in which current in the coil 92 is built up as indicated by arrow 100, a freewheel mode in which current circulates freely as indicated by arrow 102, and then may be switched off. The reversely connected FETs allow both short circuits to be prevented in the energize mode and allow the coil to be rapidly switched off. In spite of the control circuitry being formed in a common substrate with some of the FETs, the arrangement allows the FETs to be properly driven.
摘要翻译：诸如电磁线圈92的感性负载的驱动器包括三个FET 4,6,8。两个FET反向连接在电池和输出端子16,18之间，其中一个FET连接在输出和接地端子16,14之间。具有高低侧控制电路58,56的驱动电路10形成在具有两个FET 4,6的共用衬底。在使用中，线圈92连接到输出端子16，并且以如箭头100所示的线圈92中的电流被构建的通电模式被驱动，其中电流如箭头102所示自由地循环，然后可以关闭。反向连接的FET允许在通电模式下防止短路，并允许线圈快速关断。尽管控制电路形成在具有一些FET的公共衬底中，但是这种布置允许FET被适当地驱动。

4. 发明申请

US20090212846A1 Insulated gate field effect transistors 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US20090212846A1
公开(公告)日：2009-08-27
申请号：US11658224
申请日：2005-07-18
申请人： John R. Cutter
发明人： John R. Cutter
IPC分类号： H03K17/687 , H01L29/78
CPC分类号： H01L29/7802 , H01L27/0251 , H01L29/41766 , H01L29/4238 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.
摘要翻译：场晶体管被分成多个单元（6），并且包括连接到第一晶体管单元（8）的单独的第一栅极线（20）和连接到第二晶体管单元（10）的单独的第二栅极线（22）。驱动电路用于在正常饱和操作状态下驱动所有单元（6），但是在线性操作状态仅驱动第二单元（10）以减少在线性操作状态中使用的单元数量。

5. 发明授权

US06724093B2 Semiconductor devices and their manufacture 失效
标题翻译：半导体器件及其制造
公开(公告)号：US06724093B2
公开(公告)日：2004-04-20
申请号：US09912142
申请日：2001-07-24
申请人： John R. Cutter
发明人： John R. Cutter
IPC分类号： H01L2348
CPC分类号： H01L23/60 , H01L23/49562 , H01L23/562 , H01L23/585 , H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05624 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01078 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/351 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device. The ductile metal layer pattern (50) reduces stress between the insulating material (40) and the plastic material (100), but it can be both easily and cheaply applied in device manufacture before dividing the wafer into individual chips.
摘要翻译：热循环可能导致封装在合成树脂材料（100）中的半导体器件芯片（10）的上表面受到破坏，特别是在包括IC的功率器件的情况下。本发明在芯片（10）的绝缘覆层（40）的大部分顶表面上提供例如铝的厚的延性层图案（50）。这种延展性覆盖物的电隔离部分（50a，50b，50c，50d等）分别连接到相应的底部导电区域，以便减少穿过绝缘层（40）的充电效应。在这些隔离部分（50a，50b，50c，50d等）之间存在足够的间隔Z1，以避免由于在装置的热循环期间的剪切和拖尾而变形而导致短路。延展金属层图案（50）减小了绝缘材料（40）和塑料材料（100）之间的应力，但是在将晶片分成单个芯片之前，可以容易且便宜地将其应用于器件制造。

6. 发明授权

US06498071B2 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US06498071B2
公开(公告)日：2002-12-24
申请号：US09725410
申请日：2000-11-29
申请人： Erwin A. Hijzen , Cornelis E. Timmering , John R. Cutter
发明人： Erwin A. Hijzen , Cornelis E. Timmering , John R. Cutter
IPC分类号： H01L2176
CPC分类号： H01L29/66848 , H01L29/66348 , H01L29/66666
摘要： In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11′) is provided in a trench (20) with a trench etchant mask (51, FIG. 2) still present so that the gate material (11′) forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, FIG. 5), and the gate (11) is then provided with an insulating overlayer (18, FIG. 6). Forming the sidewall spacer (32) when the protruding trench-gate structure has a well-defined edge provided by the gate material (11′) allows better definition of the source region (13) compared with a prior-art process in which the gate insulating overlayer is provided in the trench before causing the trench-gate structure to have the protruding step for the sidewall spacer.
摘要翻译：在制造沟槽栅极半导体器件例如MOSFET或IGBT时，起始半导体本体（10）具有两个用于形成源极和体区的顶层（13,15）。栅极材料（11'）设置在沟槽（20）中，其沟槽蚀刻剂掩模（图2中的51）仍然存在，使得栅极材料（11'）从邻近的表面（10a）形成突出的台阶（30）），并且在步骤（30）中形成侧壁间隔物（32）以更换掩模（51）。源极区域（13）与突出的沟槽栅极结构自对准形成，具有由间隔物（图5中的32）确定的横向范围，并且栅极（11）然后设置有绝缘覆盖层（18，图6）。当突出的沟槽栅极结构具有由栅极材料（11'）提供的良好限定的边缘时，形成侧壁间隔物（32）允许源区域（13）的更好的定义与现有技术的工艺相比，其中栅极在使沟槽栅结构具有侧壁间隔物的突出步骤之前，在沟槽中设置绝缘覆层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式