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1. 发明申请

US20220100575A1 METHOD AND APPARATUS FOR A CONFIGURABLE HARDWARE ACCELERATOR 有权
公开(公告)号：US20220100575A1
公开(公告)日：2022-03-31
申请号：US17032103
申请日：2020-09-25
申请人： Chang Hoon LEE , Paul ALEPIN , John Edward VINCENT
发明人： Chang Hoon LEE , Paul ALEPIN , John Edward VINCENT
IPC分类号： G06F9/50 , G06F3/06 , G06F13/28
摘要： Method and apparatus for process accelerator (PA) using configurable hardware accelerators is provided. The PA can include a plurality of processing elements (PEs). The PEs of the PA can be used to accelerate a process and/or one or more threads. PEs can include PE local memory which due to the memories' close physical proximity to the PE can result in reduced energy consumption. The plurality of PEs can be daisy-chain connected or DMA mode can be used to write the result of a PE directly into the PE local memory of another PE for further processing.

2. 发明授权

US06359884B1 Modular scalable packet scheduler with rate based shaping and virtual port scheduler 失效
标题翻译：模块化可扩展数据包调度程序，具有基于速率的整形和虚拟端口调度器
公开(公告)号：US06359884B1
公开(公告)日：2002-03-19
申请号：US09105469
申请日：1998-06-26
申请人： John Edward Vincent
发明人： John Edward Vincent
IPC分类号： H04L1228
CPC分类号： H04L47/10 , H04L49/3081 , H04L2012/5679
摘要： A partitioned packet scheduler comprising a queue manager, an optionally connected rate shaper, and an optionally connected virtual port scheduler is provided. The packet scheduler is for use in a packet switch and has a very simple interface with the remainder of the switch consisting a channel for communicating buffer addresses and internal connection numbers. Very simple interfaces also exist between the queue manager and the rate shaper/virtual port scheduler thereby allowing independent design and update of these components to be performed.
摘要翻译：提供了包括队列管理器，可选连接的速率整形器和可选地连接的虚拟端口调度器的分区分组调度器。分组调度器用于分组交换机，并且具有非常简单的接口，其中交换机的其余部分包括用于传送缓冲器地址和内部连接号码的通道。队列管理器和速率整形器/虚拟端口调度器之间也存在非常简单的接口，从而允许执行这些组件的独立设计和更新。

3. 发明授权

US10761560B2 Method and apparatus for transaction based propagated clock-gating for low power design 有权
公开(公告)号：US10761560B2
公开(公告)日：2020-09-01
申请号：US16160075
申请日：2018-10-15
申请人： Chang Hoon Lee , John Edward Vincent , Louis-Philippe Hamelin , Paul Alepin
发明人： Chang Hoon Lee , John Edward Vincent , Louis-Philippe Hamelin , Paul Alepin
IPC分类号： G06F1/10 , H03K5/135 , G06F30/327 , G06F119/06 , G06F119/12
摘要： The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

4. 发明授权

US06118764A Congestion indication/no increase (CI/NI) ABR flow control for ATM switches 失效
标题翻译： ATM交换机的拥塞指示/不增加（CI / NI）ABR流量控制
公开(公告)号：US06118764A
公开(公告)日：2000-09-12
申请号：US550
申请日：1997-12-30
申请人： Gary Michael Depelteau , John Edward Vincent , Abdulaziz Almulhem
发明人： Gary Michael Depelteau , John Edward Vincent , Abdulaziz Almulhem
IPC分类号： H04L12/70 , H04Q11/04 , G01R31/08
CPC分类号： H04Q11/0478 , H04L2012/563 , H04L2012/5635 , H04L2012/5636 , H04L2012/5651
摘要： A system and method for updating the congestion indication and no increase values in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. The values are set according to the underutilization or over utilization of the allocated elastic bandwidth.
摘要翻译：一种用于在异步传输模式网络中的可用比特率连接上更新拥塞指示并且不增加资源管理小区中的增加值的系统和方法。该方法确定每端口弹性可分配速率作为端口容量的函数，以及当前高优先级流量速率。这些值是根据分配的弹性带宽的利用不足或过度利用来设定的。

5. 发明申请

US20200117231A1 METHOD AND APPARATUS FOR TRANSACTION BASED PROPAGATED CLOCK-GATING FOR LOW POWER DESIGN 审中-公开
公开(公告)号：US20200117231A1
公开(公告)日：2020-04-16
申请号：US16160075
申请日：2018-10-15
申请人： Chang Hoon LEE , John Edward VINCENT , Louis-Philippe HAMELIN , Paul ALEPIN
发明人： Chang Hoon LEE , John Edward VINCENT , Louis-Philippe HAMELIN , Paul ALEPIN
IPC分类号： G06F1/10 , G06F17/50 , H03K5/135
摘要： The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

6. 发明授权

US06643285B1 Message based packet switch based on a common, generic bus medium for transport 失效
标题翻译：基于消息的分组交换机，基于通用的通用总线介质进行传输
公开(公告)号：US06643285B1
公开(公告)日：2003-11-04
申请号：US09024243
申请日：1998-02-17
申请人： John Edward Vincent , George F. Irwin , Gary M. Depelteau , Tony Huang , David A. Fisher , James L. Watchorn , Melhem I. Chaar
发明人： John Edward Vincent , George F. Irwin , Gary M. Depelteau , Tony Huang , David A. Fisher , James L. Watchorn , Melhem I. Chaar
IPC分类号： H04L1256
CPC分类号： H04L49/255 , H04L49/15 , H04L49/1553 , H04L49/30 , H04L49/503
摘要： A packet switch has a switching unit (SU) for switching packets between network links and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU. The SU is formed of different functional components interconnected by generic buses. The components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol. The communication between the components occurs by placing PDUs in bus frames that are passed from component to component. Information is exchanged between the components by adding information to or dropping information from the fields of the PDUs, or by concatenating new fields to the PDUs, as the frames pass from component to component. By using a generic bus to implement PDU-based interconnections within the SU, all the components are forced to support a common interface. Changes to the implementations of any component's interface can thus be accommodated by changing the PDU format as opposed to changing the interfaces of connected components. The new packet switch architecture decouples the components on the switch so that they can be upgraded or otherwise modified independently of one another.
摘要翻译：分组交换机具有用于在网络链路之间切换分组的交换单元（SU）和通过网络链路连接到SU的计算单元（CU），用于在SU上实现软件控制功能。 SU由通用总线互连的不同功能部件组成。组件使用根据共享设备协议格式化和传输的程序数据单元（PDU）彼此通信。通过将PDU放置在从组件传递到组件的总线框架中，可以实现组件之间的通信。通过向PDU中的信息添加信息或从PDU的字段中删除信息，或者通过将新的字段连接到PDU来在组件之间交换信息，因为帧从组件传递到组件。通过使用通用总线来实现SU内的基于PDU的互连，所有组件都被迫支持通用接口。因此，可以通过改变PDU格式来改变任何组件接口的实现，而不是改变连接的组件的接口。新的分组交换架构使交换机上的组件脱钩，以便它们可以彼此独立升级或以其他方式进行修改。

7. 发明授权

US06438132B1 Virtual port scheduler 有权
标题翻译：虚拟端口调度器
公开(公告)号：US06438132B1
公开(公告)日：2002-08-20
申请号：US09170973
申请日：1998-10-14
申请人： John Edward Vincent , James Leslie Watchorn
发明人： John Edward Vincent , James Leslie Watchorn
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L47/2425 , H04L47/50 , H04L47/621 , H04L2012/5679 , H04Q11/0478
摘要： A virtual port scheduler is provided optionally for inclusion as part of a partitioned packet scheduler comprising a queue manager. The virtual port scheduler maintains a plurality of statuses for remote ports which do not have their own scheduling functionality. On the basis of those statuses, the virtual port scheduler determines which virtual port to service next.
摘要翻译：可选地提供虚拟端口调度器作为包括队列管理器的分区分组调度器的一部分。虚拟端口调度器为不具有其自己的调度功能的远程端口维护多个状态。在这些状态的基础上，虚拟端口调度器确定接下来要服务的虚拟端口。

8. 发明授权

US06262985B1 Method and apparatus for full range translation of large external identifier to small internal identifier 失效
标题翻译：用于将大型外部标识符全范围转换为小型内部标识符的方法和装置
公开(公告)号：US06262985B1
公开(公告)日：2001-07-17
申请号：US09050129
申请日：1998-03-30
申请人： Tony Huang , John Edward Vincent , James Leslie Watchorn , Paul Fong-Yan Hung , Osama Bahgat , Gary Depelteau , James McLaughlin
发明人： Tony Huang , John Edward Vincent , James Leslie Watchorn , Paul Fong-Yan Hung , Osama Bahgat , Gary Depelteau , James McLaughlin
IPC分类号： H04L1250
CPC分类号： H04L49/309 , H04L45/742 , H04Q11/0478
摘要： Methods and apparatus are described for translating identifiers that are used by computers to reference various entities such as data structures, external objects, or connections in a telecommunications network, from a bulkier less manageable format to a smaller more manageable format. Such translations are carried out to reduce the needless processing and memory demands that are made of a localized set of components when the large identifiers the set receives from other components include fields that none of the members of the set need to access. The invention is centerd around a two-stage look-up method wherein an inputted external identifier is divided into two parts. The first part of the inputted external identifier is used as an address into a first look-up table that contains base-addresses of a second look-up table. The second part of the inputted external identifier is used as an offset-address into the second look-up table. The offset-address and the base-address are combined to access the second look-up table, which contains all the internal identifiers. The invention can be easily scaled to handle a larger range of external identifiers, and a larger number of internal identifiers. The invention operates at a fast and predictable speed. Use of the invention also leads to a significant savings in memory costs.
摘要翻译：描述了用于翻译计算机使用的标识符的方法和装置，以引用各种实体，例如电信网络中的数据结构，外部对象或连接，从庞大的较不易管理的格式到更小的更易于管理的格式。执行这样的翻译以减少当集合从其他组件接收到的大标识符包括集合中的任何成员都不需要访问的字段时，由本地化的组件集合形成的不必要的处理和存储器需求。本发明围绕两阶段查找方法，其中输入的外部标识符被分成两部分。输入的外部标识符的第一部分用作包含第二查找表的基地址的第一查找表中的地址。输入的外部标识符的第二部分用作第二查找表中的偏移地址。偏移地址和基地址被组合以访问包含所有内部标识符的第二查找表。本发明可以容易地缩放以处理更大范围的外部标识符和更大数量的内部标识符。本发明以快速且可预测的速度运行。使用本发明还可显着节省存储器成本。

9. 发明授权

US6115359A Elastic bandwidth explicit rate (ER) ABR flow control for ATM switches 失效
标题翻译： ATM交换机的弹性带宽显式速率（ER）ABR流量控制
公开(公告)号：US6115359A
公开(公告)日：2000-09-05
申请号：US548
申请日：1997-12-30
申请人： Gary Michael Depelteau , John Edward Vincent , Abdulaziz Almulhem
发明人： Gary Michael Depelteau , John Edward Vincent , Abdulaziz Almulhem
IPC分类号： H04L12/70 , H04Q11/04 , G01R31/08 , H04L12/28
CPC分类号： H04Q11/0478 , H04L2012/5635
摘要： A system and method for updating the explicit rate in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. A steering factor is used which is iteratively increased or decreased according to the underutilization or over utilization of the allocated elastic bandwidth.
摘要翻译：一种用于在异步传输模式网络中的可用比特率连接上更新资源管理小区中的显式速率的系统和方法。该方法确定每端口弹性可分配速率作为端口容量的函数，以及当前高优先级流量速率。使用根据分配的弹性带宽的不充分利用或过度利用迭代地增加或减少的转向因子。

10. 发明授权

US06404767B1 Architecture for ABR processing within an ATM switch 失效
标题翻译： ATM交换机内ABR处理的架构
公开(公告)号：US06404767B1
公开(公告)日：2002-06-11
申请号：US09098491
申请日：1998-06-17
申请人： Gary Michael Depelteau , John Edward Vincent
发明人： Gary Michael Depelteau , John Edward Vincent
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L2012/5635 , H04L2012/5636 , H04L2012/568
摘要： Systems and methods for implementing ABR (available bit rate) flow control in ATM (asynchronous transfer mode switches are provided. A partitioned architecture a featuring standalone ABR processing subsystem advantageously allows components to be changed with little impact on the switch's overal design. Both end-to-end and VS/VD (virtual source/virtual destination) flow control systems are provided as are both configurations for switches which are either standalone or connected to a switching fabric.
摘要翻译：在ATM中实现ABR（可用比特率）流控制的系统和方法（异步传输模式交换机），具有独立ABR处理子系统的分区架构有利于允许组件更改，对交换机的外部设计影响不大，端到端和VS / VD（虚拟源/虚拟目的地）流控制系统都是独立的或连接到交换结构的交换机的配置。

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