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1. 发明授权

US08686535B2 Trench isolation implantation 有权
标题翻译：沟槽隔离植入
公开(公告)号：US08686535B2
公开(公告)日：2014-04-01
申请号：US12758488
申请日：2010-04-12
申请人： Gurtej S. Sandhu , John A. Smythe, III
发明人： Gurtej S. Sandhu , John A. Smythe, III
IPC分类号： H01L21/70
CPC分类号： H01L21/76237 , G11C11/401 , H01L27/10844 , H01L27/11517
摘要： Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.
摘要翻译：本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

2. 发明授权

US07622769B2 Isolation trench 有权
标题翻译：隔离槽
公开(公告)号：US07622769B2
公开(公告)日：2009-11-24
申请号：US11497665
申请日：2006-08-01
申请人： John A. Smythe, III , Jigish D. Trivedi
发明人： John A. Smythe, III , Jigish D. Trivedi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。然后沉积可膨胀的可氧化衬垫，优选非晶硅。然后用旋涂电介质（SOD）材料填充沟槽。然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。优选地，在致密化过程的至少部分期间，温度升高而氧化。所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

3. 发明授权

US07271463B2 Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base 有权
标题翻译：沟槽绝缘结构包括沿着沟槽的壁比沿底部更薄的氧化物衬垫
公开(公告)号：US07271463B2
公开(公告)日：2007-09-18
申请号：US11009665
申请日：2004-12-10
申请人： John A. Smythe, III , William Budge
发明人： John A. Smythe, III , William Budge
IPC分类号： H01L23/58
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。然后在沟槽上进行各向异性等离子体处理。在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。然后用旋涂前体填充沟槽。然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。

4. 发明申请

US20120001144A1 RESISTIVE RAM DEVICES AND METHODS 有权
公开(公告)号：US20120001144A1
公开(公告)日：2012-01-05
申请号：US12830079
申请日：2010-07-02
申请人： Joseph N. Greeley , John A. Smythe, III
发明人： Joseph N. Greeley , John A. Smythe, III
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1633
摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

5. 发明授权

US07659181B2 Sub-micron space liner and filler process 有权
标题翻译：亚微米空间衬垫和填料工艺
公开(公告)号：US07659181B2
公开(公告)日：2010-02-09
申请号：US11557014
申请日：2006-11-06
申请人： John A. Smythe, III , Jigish D. Trivedi
发明人： John A. Smythe, III , Jigish D. Trivedi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。然后沉积可膨胀的可氧化衬垫，优选非晶硅。然后用旋涂电介质（SOD）材料填充沟槽。然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。优选地，在致密化过程的至少部分期间，温度升高而氧化。所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

6. 发明授权

US07521378B2 Low temperature process for polysilazane oxidation/densification 有权
公开(公告)号：US07521378B2
公开(公告)日：2009-04-21
申请号：US10883191
申请日：2004-07-01
申请人： Janos Fucsko , John A Smythe, III , Li Li , Grady S Waldo
发明人： Janos Fucsko , John A Smythe, III , Li Li , Grady S Waldo
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02236 , H01L21/02282 , H01L21/02343 , H01L21/3125 , H01L21/316 , H01L21/76205 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832
摘要： Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

7. 发明授权

US07501691B2 Trench insulation structures including an oxide liner and oxidation barrier 有权
标题翻译：包括氧化物衬垫和氧化屏障的沟槽绝缘结构
公开(公告)号：US07501691B2
公开(公告)日：2009-03-10
申请号：US11846041
申请日：2007-08-28
申请人： John A. Smythe, III , William Budge
发明人： John A. Smythe, III , William Budge
IPC分类号： H01L23/58
CPC分类号： H01L21/76224
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。然后在沟槽上进行各向异性等离子体处理。在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。然后用旋涂前体填充沟槽。然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。

8. 发明授权

US06573141B1 In-situ etch and pre-clean for high quality thin oxides 有权
标题翻译：高质量薄氧化物的原位蚀刻和预清洁
公开(公告)号：US06573141B1
公开(公告)日：2003-06-03
申请号：US09267327
申请日：1999-03-12
申请人： Bernice L. Kickel , John A. Smythe, III
发明人： Bernice L. Kickel , John A. Smythe, III
IPC分类号： H01L21336
CPC分类号： H01L21/02052 , H01L21/28273 , H01L29/42364
摘要： The present invention provides a method for improving the quality of thin oxides formed upon a semiconductor body. The etch and pre-clean processes are performed in situ, taking place in a single apparatus. This reduces the amount of handling of the wafers, their exposure to clean room air, and time delays between clean and oxidation. This results in both a higher yield and greater reliability. In addition, it reduces equipment requirements. The etch, employing a buffered oxide etchant, resist strip, and pre-clean, all occur in a single apparatus without transfer, yielding better results, despite the inherently dirty nature of the resist strip, than the traditional technique of transferring to a new apparatus for each of these steps. The improvements are particularly important for thin oxides such as the tunnel oxides of EEPROMs.
摘要翻译：本发明提供一种提高形成在半导体本体上的薄氧化物的质量的方法。蚀刻和预清洁过程在原位进行，发生在单个设备中。这减少了晶片的处理量，它们暴露于洁净室内空气以及清洁和氧化之间的时间延迟。这导致更高的产量和更高的可靠性。此外，它减少了设备要求。使用缓冲氧化物蚀刻剂，抗蚀剂条和预清洁的蚀刻都全部发生在单个设备中而不进行转印，尽管抗蚀剂条的本质上是脏的性质，但是传递到新的设备的传统技术对于这些步骤中的每一个。这些改进对于诸如EEPROM的隧道氧化物的薄氧化物尤其重要。

9. 发明授权

US6165846A Method of eliminating gate leakage in nitrogen annealed oxides 有权
标题翻译：消除氮退火氧化物中的栅极泄漏的方法
公开(公告)号：US6165846A
公开(公告)日：2000-12-26
申请号：US260913
申请日：1999-03-02
申请人： Timothy K. Carns , John A. Smythe, III , John A. Ransom , Bernice L. Kickel , John E. Berg
发明人： Timothy K. Carns , John A. Smythe, III , John A. Ransom , Bernice L. Kickel , John E. Berg
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28202 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/518
摘要： The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.
摘要翻译：用于EEPROM和FLASH技术的薄隧道氧化物的改进使用氮中的后氧化退火在随后的氧化膜中引起缺陷。这些表现为鸟喙处的氧化物变薄，导致高漏电。随着后氧化退火的时间和温度增加，隧道氧化物性能的提高，缺陷数量迅速增加。示出了使用更高的后氧化时间和温度退火实现改进的隧道氧化物QBD的方法，同时不降低随后的栅极氧化物的质量。描述了在晶体管栅极氧化之前使用牺牲氧化和条带。该工艺除去存在于场边缘的附加氮化物，导致氧化物变薄。结果，可以在不降低高压和低压晶体管的情况下实现改进的隧道氧化物完整性。

10. 发明授权

US08324065B2 Resistive memory and methods of processing resistive memory 有权
标题翻译：电阻记忆和处理电阻记忆的方法
公开(公告)号：US08324065B2
公开(公告)日：2012-12-04
申请号：US13226950
申请日：2011-09-07
申请人： Gurtej S. Sandhu , John A. Smythe, III
发明人： Gurtej S. Sandhu , John A. Smythe, III
IPC分类号： H01L21/20 , H01L29/00
CPC分类号： H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.
摘要翻译：本文描述了电阻存储器和处理电阻性存储器的方法。处理电阻性存储器的一个或多个方法实施例包括在层间电介质的开口中共形形成电池材料，使得在电池材料中形成接缝，通过改变接缝形成导电通路，并在电池材料上形成电极和接缝。

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