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1. 发明授权

US06329245B1 Flash memory array structure with reduced bit-line pitch 失效
标题翻译：闪存阵列结构具有降低的位线间距
公开(公告)号：US06329245B1
公开(公告)日：2001-12-11
申请号：US09467116
申请日：1999-12-20
申请人： Jin Da , Sung Rae Kim , Anqing Zhang
发明人： Jin Da , Sung Rae Kim , Anqing Zhang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method is provided for the creation of floating gates of a flash memory array. The floating gates of conventional flash memory devices are formed using a single polysilicon deposition followed by a single polysilicon etch. The invention provides a method that allows for the reduction in the spacing between adjacent floating gates by providing a double polysilicon deposition followed by a double polysilicon etch process. The process of the invention starts with the formation of FOX regions in a semiconductor surface; the channel regions of the devices are implanted. The first half of the floating gates of the device are formed followed by the formation of the second half of the floating gates of the device. The control gate of the device is formed as a last step of the processes of the invention.
摘要翻译：提供了一种用于创建闪存阵列的浮动栅极的新方法。常规闪存器件的浮动栅极是使用单个多晶硅沉积形成的，随后是单个多晶硅蚀刻。本发明提供一种方法，其允许通过提供双重多晶硅沉积以及双重多晶硅蚀刻工艺来减小相邻浮栅之间的间距。本发明的过程开始于在半导体表面中形成FOX区域; 植入通道区域。形成装置的浮动栅极的前半部分，然后形成装置的浮动栅极的后半部分。该装置的控制门形成为本发明方法的最后一步。

2. 发明申请

US20120146123A1 SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：可控闪存EEPROM存储单元，带有浮动栅极间隔器，由控制门和制造方法
公开(公告)号：US20120146123A1
公开(公告)日：2012-06-14
申请号：US13361937
申请日：2012-01-30
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/11521 , H01L29/40114 , H01L29/42328
摘要： A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer.
摘要翻译：闪存单元包括在表面区域上具有表面区域和闪存单元结构的基板。闪存单元结构包括表面区域上的栅极介电层，栅极电介质层上的选择栅极，选择栅极上的覆盖氧化物层，选择栅极的第一边缘上的氧化物隔离层，第一区域和表面区域的第二区域。第二个地区是一个活跃的地区。闪存单元结构还包括在氧化物隔离物的第一边缘上的多隔离物和第一区域上的隧道氧化物层的一部分，至少在多隔离物上的ONO层和ONO层上的控制栅极层。

3. 发明授权

US08119479B2 Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate and method of manufacture 有权
标题翻译：具有浮动栅极隔离器的可扩展闪存EEPROM存储单元，由控制门和制造方法包裹
公开(公告)号：US08119479B2
公开(公告)日：2012-02-21
申请号：US12887496
申请日：2010-09-21
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328
摘要： A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.
摘要翻译：作为闪存器件的浮动栅极的多晶硅间隔物。这种间隔结构的优点是减小单元尺寸，这对于最先进的闪速存储器技术是期望的。在优选实施例中，浮动栅极可以自对准到电池选择晶体管的选择栅极的附近和/或附近。在优选实施例中，本发明在去除之后使用干蚀刻保留了在选择晶体管栅极的漏极侧上的多晶硅间隔物结构的隧道氧化物层。更优选地，本方法提供一定量的隧道氧化物以保留，以防止存储单元的漏极区域中的活性硅区域被干蚀刻气体蚀刻。

4. 发明申请

US20110089479A1 SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE 有权
标题翻译：可控闪存EEPROM存储单元，带有浮动栅极间隔器，由控制门和制造方法
公开(公告)号：US20110089479A1
公开(公告)日：2011-04-21
申请号：US12887496
申请日：2010-09-21
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328
摘要： A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.
摘要翻译：作为闪存器件的浮动栅极的多晶硅间隔物。这种间隔结构的优点是减小单元尺寸，这对于最先进的闪速存储器技术是期望的。在优选实施例中，浮动栅极可以自对准到电池选择晶体管的选择栅极的附近和/或附近。在优选实施例中，本发明在去除之后使用干蚀刻保留了在选择晶体管栅极的漏极侧上的多晶硅间隔物结构的隧道氧化物层。更优选地，本方法提供一定量的隧道氧化物以保留，以防止存储单元的漏极区域中的活性硅区域被干蚀刻气体蚀刻。

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