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1. 发明授权

US5465409A Radio architecture with dual frequency source selection 失效
标题翻译：无线电架构采用双频源选择
公开(公告)号：US5465409A
公开(公告)日：1995-11-07
申请号：US206704
申请日：1994-03-07
申请人： Jaime A. Borras , Mark J. Chambers , Jesus S. Pena Finol , Armando J. Gonzalez , Cesar W. Carralero , Sayed H. Beladi , Levent Y. Erbora
发明人： Jaime A. Borras , Mark J. Chambers , Jesus S. Pena Finol , Armando J. Gonzalez , Cesar W. Carralero , Sayed H. Beladi , Levent Y. Erbora
IPC分类号： H04B1/40 , H04B7/26 , H04J1/00 , H04B1/44
CPC分类号： H04B1/005 , H04B1/406
摘要： A radio having two architectural platforms integrated in one integrated circuit (IC). A synthesizer controller (312) selects between an offset local oscillator (LO) synthesizer (318) and a second LO synthesizer (316) to provide a common architecture for either an Frequency Division Duplex (FDD) or Time Division Duplex (TDD) system design while providing isolation between the two frequency sources. An offset LO signal (319) is translated to an isolated LO signal 310 and combined with a main LO signal (322) to provide the FDD platform. A second LO signal (314) is translated into the isolated LO signal 310 and combined with the main LO signal (322) to provide the TDD platform. The second LO synthesizer signal (314) is common to both systems in the receive mode.
摘要翻译：具有集成在一个集成电路（IC）中的两个架构平台的无线电。合成器控制器（312）在偏移本地振荡器（LO）合成器（318）和第二LO合成器（316）之间进行选择，以提供用于频分双工（FDD）或时分双工（TDD）系统设计的公共架构同时提供两个频率源之间的隔离。偏移LO信号（319）被转换为隔离LO信号310并与主LO信号（322）组合以提供FDD平台。第二LO信号（314）被转换为隔离的LO信号310并与主LO信号（322）组合以提供TDD平台。第二LO合成器信号（314）在接收模式下对于两个系统是公共的。

2. 发明授权

US5832370A Current mode transceiver circuit and method 失效
标题翻译：电流模式收发电路及方法
公开(公告)号：US5832370A
公开(公告)日：1998-11-03
申请号：US721399
申请日：1996-09-26
申请人： Jesus S. Pena-Finol , Mark J. Chambers , Erica G. Miller , Philippe Gorisse
发明人： Jesus S. Pena-Finol , Mark J. Chambers , Erica G. Miller , Philippe Gorisse
IPC分类号： H04B15/00 , H04L25/02 , H04B1/38
CPC分类号： H04L25/0282 , H04B15/005 , H04L25/0294
摘要： A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.
摘要翻译：发射机（300）沿着发射信号路径（203,204）将发送的电流（I203，I204）发送到具有低输入阻抗的接收机（400）。接收机包括放大发射电流的晶体管结构（402,404），并将其馈送回接收机的输入端，以保持低输入阻抗和发射信号路径上基本上恒定的电压。在接收器的输入处的基本上恒定的电压避免了与沿着发射信号路径定位的其它电路（206,208）的干扰。

3. 发明授权

US5617056A Base current compensation circuit 失效
标题翻译：基极电流补偿电路
公开(公告)号：US5617056A
公开(公告)日：1997-04-01
申请号：US498038
申请日：1995-07-05
申请人： William E. Main , David K. Lovelace , Jesus S. Pena-Finol
发明人： William E. Main , David K. Lovelace , Jesus S. Pena-Finol
IPC分类号： G05F3/26 , G05F1/10
CPC分类号： G05F3/265
摘要： A base current compensation circuit (10) generates a current that tracks a gain of a transistor (11). The compensation circuit (10) includes a current mirror formed by a mirror transistor (12) and an output transistor (14). The mirror transistor (12) is connected to the transistor (11) whose gain is tracked. A current source (16) and a feedback transistor (13) causes the mirror transistor (12) to draw a base current from the transistor (11) so that a collector current of the transistor (11) matches a reference current. The output transistor (14) amplifies the base current of the transistor (11) to generate the tracking current in the collector electrode of the output transistor (14).
摘要翻译：基极电流补偿电路（10）产生跟踪晶体管（11）的增益的电流。补偿电路（10）包括由镜晶体管（12）和输出晶体管（14）形成的电流镜。镜晶体管（12）连接到其增益被跟踪的晶体管（11）。电流源（16）和反馈晶体管（13）使得反射镜晶体管（12）从晶体管（11）抽取基极电流，使得晶体管（11）的集电极电流与参考电流相匹配。输出晶体管（14）放大晶体管（11）的基极电流，以在输出晶体管（14）的集电极中产生跟踪电流。

4. 发明授权

US5381114A Continuous time common mode feedback amplifier 失效
标题翻译：连续时间共模反馈放大器
公开(公告)号：US5381114A
公开(公告)日：1995-01-10
申请号：US223416
申请日：1994-04-04
申请人： Jesus S. Pena-Finol , Mark J. Chambers , James B. Phillips
发明人： Jesus S. Pena-Finol , Mark J. Chambers , James B. Phillips
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/45641
摘要： A continuous time common mode feedback amplifier CTCMFB (300) is suitable for applications requiring fully differential amplifiers in low voltage supply requirements. Two mirror image, low gain CMOS amplifiers (MP0/MP2 and MP3/MP4) in the CTCMFB (300) define and stabilize the common mode output voltage, Vcm, of the main differential amplifier (102). The transient response of the common mode amplifier (300) can be adjusted independently of the transient response of the main differential amplifier (102), allowing fast transient response to the main differential amplifier.
摘要翻译：连续时间共模反馈放大器CTCMFB（300）适用于要求低电压电源要求的全差分放大器的应用。 CTCMFB（300）中的两个镜像，低增益CMOS放大器（MP0 / MP2和MP3 / MP4）定义并稳定主差分放大器（102）的共模输出电压Vcm。可以独立于主差分放大器（102）的瞬态响应来调节共模放大器（300）的瞬态响应，允许对主差分放大器的快速瞬态响应。

5. 发明授权

US4546275A Quarter-square analog four-quadrant multiplier using MOS integrated circuit technology 失效
标题翻译：使用MOS集成电路技术的四分之一平方的模拟四象限乘法器
公开(公告)号：US4546275A
公开(公告)日：1985-10-08
申请号：US500540
申请日：1983-06-02
申请人： Jesus S. Pena-Finol , Joseph A. Connelly
发明人： Jesus S. Pena-Finol , Joseph A. Connelly
IPC分类号： G06G7/164 , H03K5/22
CPC分类号： G06G7/164
摘要： A four-quadrant NMOS transconductance multiplier including plural NMOS transistors formed in a substrate to produce a pair of summer stages and a pair of squaring stages which process a pair of input signals V.sub.1, V.sub.2 to produce an output signal V.sub.o according to the quarter-square algebraic identity,V.sub.o =1/4[(V.sub.1 +V.sub.2).sup.2 -(V.sub.1 -V.sub.2).sup.2 ]=V.sub.1 V.sub.2.In a preferred embodiment, the substrate doping N.sub.A =6.7.times.10.sup.15 cm.sup.-3 and the channel width and channel length of each of the NMOS transistors forming the summer and squaring stages is greater than 10 .mu.m.
摘要翻译：一个四象限的NMOS跨导乘法器，包括形成在衬底中的多个NMOS晶体管，以产生一对加法级，并且一对平方根处理一对输入信号V1，V2以产生根据四分之一平方的输出信号Vo 代数识别，Vo = 1/4 [（V1 + V2）2-（V1-V2）2] = V1V2。在优选实施例中，掺杂NA = 6.7×10 15 cm -3的衬底以及形成夏季和平方级的每个NMOS晶体管的沟道宽度和沟道长度大于10微米。

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