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1. 发明授权

US08229683B2 Test circuit for bias temperature instability recovery measurements 有权
标题翻译：用于偏置温度不稳定性恢复测量的测试电路
公开(公告)号：US08229683B2
公开(公告)日：2012-07-24
申请号：US12962726
申请日：2010-12-08
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L1/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

2. 发明授权

US08154309B2 Configurable PSRO structure for measuring frequency dependent capacitive loads 失效
标题翻译：可配置的PSRO结构，用于测量频率相关的容性负载
公开(公告)号：US08154309B2
公开(公告)日：2012-04-10
申请号：US12489656
申请日：2009-06-23
申请人： Kanak B. Agarwal , Jerry D. Hayes
发明人： Kanak B. Agarwal , Jerry D. Hayes
IPC分类号： G01R27/26
CPC分类号： G01R31/27 , G01R31/2853
摘要： A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, CPAR. Current is measured to both the device under test (DUT) and the de-embedding structure. From these measurements, the frequency dependent capacitance of the DUT is calculated.
摘要翻译：可配置的PSRO测量电路用于通过硅通孔（TSV）或其他导电结构测量目标的频率相关电容。通过使用可调电阻和去嵌入结构来测量目标结构的测量来测量寄生电容CPAR的影响。电流被测量到被测器件（DUT）和去嵌入结构。从这些测量中，计算DUT的频率相关电容。

3. 发明申请

US20110074394A1 TEST CIRCUIT FOR BIAS TEMPERATURE INSTABILITY RECOVERY MEASUREMENTS 有权
标题翻译：用于偏温不稳定性恢复测量的测试电路
公开(公告)号：US20110074394A1
公开(公告)日：2011-03-31
申请号：US12962726
申请日：2010-12-08
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01R19/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

4. 发明申请

US20100321042A1 CONFIGURABLE PSRO STRUCTURE FOR MEASURING FREQUENCY DEPENDENT CAPACITIVE LOADS 失效
标题翻译：用于测量频率依赖电容负载的可配置的结构
公开(公告)号：US20100321042A1
公开(公告)日：2010-12-23
申请号：US12489656
申请日：2009-06-23
申请人： Kanak B. Agarwal , Jerry D. Hayes
发明人： Kanak B. Agarwal , Jerry D. Hayes
IPC分类号： G01R27/26
CPC分类号： G01R31/27 , G01R31/2853
摘要： A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, CPAR. Current is measured to both the device under test (DUT) and the de-embedding structure. From these measurements, the frequency dependent capacitance of the DUT is calculated.
摘要翻译：可配置的PSRO测量电路用于通过硅通孔（TSV）或其他导电结构测量目标的频率相关电容。通过使用可调电阻和去嵌入结构来测量目标结构的测量来测量寄生电容CPAR的影响。电流被测量到被测器件（DUT）和去嵌入结构。从这些测量中，计算DUT的频率相关电容。

5. 发明申请

US20100318313A1 MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效
标题翻译：统计应力的测量方法和阵列结构和可靠性结构测试
公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译：在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛。在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

6. 发明申请

US20090251167A1 Array-Based Early Threshold Voltage Recovery Characterization Measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

7. 发明申请

US20090160477A1 METHOD AND TEST SYSTEM FOR FAST DETERMINATION OF PARAMETER VARIATION STATISTICS 有权
标题翻译：用于快速确定参数变化统计的方法和测试系统
公开(公告)号：US20090160477A1
公开(公告)日：2009-06-25
申请号：US11961442
申请日：2007-12-20
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R31/01 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译：用于快速确定参数变化统计的方法和测试系统提供了使用低计算能力和容易获得的测试设备来确定过程变化和参数统计的机制。在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。阵列的测试输出提供依赖于特定器件参数的电流或电压。器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

8. 发明申请

US20090160463A1 CHARACTERIZATION CIRCUIT FOR FAST DETERMINATION OF DEVICE CAPACITANCE VARIATION 失效
标题翻译：用于快速确定器件电容变化的特征电路
公开(公告)号：US20090160463A1
公开(公告)日：2009-06-25
申请号：US12361891
申请日：2009-01-29
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R27/26
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译：用于快速确定器件电容变化统计的测试电路提供了一种使用低计算能力和易于获得的测试设备来确定过程变化和参数统计的机制。在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。阵列的测试输出提供依赖于特定器件参数的电流或电压。器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

9. 发明授权

US07401307B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07401307B2
公开(公告)日：2008-07-15
申请号：US10904309
申请日：2004-11-03
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

10. 发明授权

US06487701B1 System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效
标题翻译：通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法
公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
申请人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
发明人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译：描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移，孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。

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