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1. 发明授权

US4580265A Failure detection method and apparatus 失效
标题翻译：故障检测方法及装置
公开(公告)号：US4580265A
公开(公告)日：1986-04-01
申请号：US509699
申请日：1983-06-30
申请人： David N. Gooding , Stefan P. Jackowski , James T. Moyer , James W. Plant, III
发明人： David N. Gooding , Stefan P. Jackowski , James T. Moyer , James W. Plant, III
IPC分类号： H04L1/00 , G06F11/10
CPC分类号： G06F11/10
摘要： A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.
摘要翻译：故障检测装置检测电路中是否存在异常电路状况，该电路使随后发送的数据字节相对于先前发送的数据字节从一个集成电路发送到另一个集成电路。偶数和奇数数据字节由具有奇校验的第一集成电路接收。然而，偶数数据字节从具有奇数奇偶校验的集成电路之间沿现有接口线传输从第一集成电路传输到第二集成电路。奇数数据字节的奇偶校验位反转，奇数数据字节沿现有的接口线以偶校验发送。第二集成电路中的异或门接收偶数数据字节的奇偶校验位，并响应于来自奇数锁存器的时钟信号的第一状态而不反转地通过奇偶校验位; 然而，异或门在接收到奇数数据字节时响应于时钟信号的第二状态重新反转奇数数据字节的奇偶校验位。奇偶校验器将输入偶数和奇数数据字节的数据位与异或门产生的奇偶校验位进行比较，并产生一个错误检查信号，代表随后发送的数据字节的接收，该序列相对于先前传输当奇偶检验器的输入端的数据位和奇偶校验位的组合奇偶校验不是奇数时的数据字节。

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