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    • 1. 发明授权
      US5185872A System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy 失效
    • System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy
    • 通过选择性分录器登记人员执行不同周期指令的系统，如果需要资源繁忙，则取消执行有条件的指令
    • US5185872A
    • 1993-02-09
    • US486407
    • 1990-02-28
    • James M. Arnold , Glenn J. Hinton , Frank S. Smith
    • James M. Arnold , Glenn J. Hinton , Frank S. Smith
    • G06F9/22 , G06F9/32 , G06F9/38
    • G06F9/325 , G06F9/3836 , G06F9/3838
    • A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction. An instruction lacking any needed unit or a register is stopped in response to the asserted scbok line and reissued in the next cycle. Registers to be used by a multi-cycle instruction are marked busy for an instruction that is able to be executed. When a result for the multi-cycle instruction returns the registers previously marked busy are marked as not busy.
    • 扫描线在数据处理系统中连接到寄存器文件和其他单元，例如执行单元和乘法/除法单元。 记忆体线连接到寄存器文件和其他单元，诸如指令单元和存储器接口单元。 连接到scbok线的每个单元可以拉线以指示它正忙。 连接到mem sckk线的每个单元可以拉线以指示它正忙。 sclok线表示当寄存器文件中忙于上一个指令的单元或寄存器不能用于寄存器文件操作的指令时。 mem sckk行表示当一个单元或寄存器文件中的一个寄存器正在忙于上一条指令时，不能用于存储器操作的指令。 寄存器与发出指令并发检查。 没有任何所需单元或寄存器的指令将停止响应断言的跳线，并在下一个周期重新发行。 多周期指令使用的寄存器将被标记为能够被执行的指令的忙。 当多周期指令的结果返回先前标记为忙的寄存器被标记为不忙时。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5023844A Six-way access ported RAM array cell 失效
    • Six-way access ported RAM array cell
    • 六路存取端口RAM阵列单元
    • US5023844A
    • 1991-06-11
    • US486408
    • 1990-02-28
    • James M. Arnold , Glenn J. Hinton , Frank S. Smith
    • James M. Arnold , Glenn J. Hinton , Frank S. Smith
    • G11C11/413 , G11C8/16 , G11C11/401
    • G11C8/16
    • A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.
    • 具有多个独立读端口的寄存器文件中的随机访问存储单元和支持并行指令执行的多个独立写端口。 RAM单元消耗低功率，符合紧凑的布局间距，以满足随机存取存储器的需要。 使用单列线，参考现有技术的两列设计，存储锁存装置（M 11，M 12）的尺寸增加以提供噪声容限损失。 在单元锁存器（M11，M12）的相对侧附加单个n器件（M 1），以在将零写入单元之前清除单元。 要写入的寄存器首先在第一个时钟周期的PH2中清零，其中写入第二个时钟周期的PH1中的数据写入。 此时也写入零位，但是它们发现已经处于零状态的单元，已在第一个时钟周期的PH2中清零。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5613132A Integer and floating point register alias table within processor device 失效
    • Integer and floating point register alias table within processor device
    • 处理器设备内的整数和浮点寄存器别名表
    • US5613132A
    • 1997-03-18
    • US129678
    • 1993-09-30
    • David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
    • David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
    • G06F9/38 , G06F13/00
    • G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
    • A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources. Logic is provided for performing prioritized table reads in parallel for all uops and prioritized table writes in parallel for all ups. There is a separate integer and floating point RAT. Up to four uops may be processed by the RAT logic within a given clock cycle.
    • 用于在超标量微处理器内进行浮点和整数寄存器重命名的寄存器别名表（RAT）。 RAT提供整数和浮点寄存器和标志的寄存器重命名，以利用比给定宏架构（如Intel架构或Power PC或Alpha设计）中通常可用的更大的物理寄存器集，从而消除虚假的数据依赖 这降低了整体超标量处理性能。 当uops同时呈现给RAT逻辑时，它们的逻辑源（浮点和整数）被用作RAT阵列的索引，以查找驻留在重新排序缓冲器（ROB）中的相应物理寄存器，其中数据为 找到这些逻辑源。 ROB由许多多位物理寄存器组成。 在相同的时钟周期期间，RAT阵列由分配器授予的新的物理目的地进行更新，使得在未来的周期中的uops可以读取它们的物理源。 提供逻辑用于对于所有的并行执行所有的uop并行执行优先级表读取并且对于所有的并行执行优先级表的写入。 有一个单独的整数和浮点RAT。 在给定的时钟周期内，最多可以由RAT逻辑处理四个Uops。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5499352A Floating point register alias table FXCH and retirement floating point register array 失效
    • Floating point register alias table FXCH and retirement floating point register array
    • 浮点寄存器别名表FXCH和退出浮点寄存器数组
    • US5499352A
    • 1996-03-12
    • US129687
    • 1993-09-30
    • David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
    • David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
    • G06F9/315 , G06F9/38 , G06F12/02 , G06F9/30 , G06F15/31
    • G06F9/30032 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , Y10S707/99936
    • A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to another floating point RAT array. The retirement floating point RAT array is updated only upon uop retirement whereas the floating point RAT array is updated at uop issuance.
    • 一个注册别名表（RAT），包括一个退休浮点RAT阵列，用于在能够进行推测执行的超标量微处理器中重新命名的浮点寄存器。 RAT提供寄存器重命名浮点寄存器，以利用比给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）中通常可用的更大的物理寄存器集，从而消除虚假数据依赖性，从而减少整体 超标量加工性能。 当将一组uops呈现给浮点RAT逻辑时，它们的逻辑源用作浮点RAT阵列的索引，以查找驻留在重新排序缓冲器（ROB）内的对应物理寄存器，其中这些数据为 发现逻辑来源。 通过切换6位物理寄存器指针，而不是切换86位宽的每个物理寄存器的实际数据，在浮点RAT机制内实现高效的FXCH操作。 存在具有双有效位的退休浮点RAT阵列和双TOS指针，以考虑另外的浮点RAT阵列之外的推测性FXCH操作。 退休浮点RAT阵列仅在Uop退出时更新，而浮点RAT阵列在uop发行时被更新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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