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1. 发明授权

US06592269B1 Apparatus and method for integrating an optical transceiver with a surface mount package 失效
标题翻译：用于将光收发器与表面安装封装集成的装置和方法
公开(公告)号：US06592269B1
公开(公告)日：2003-07-15
申请号：US09944856
申请日：2001-08-31
申请人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
发明人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
IPC分类号： G02B636
CPC分类号： G02B6/4246 , G02B6/4253 , G02B6/4269 , G02B6/4274 , G02B6/428 , G02B6/4283
摘要： An apparatus and method integrates optical transceivers for transfer of signals between optical and electronic media with surface mount packages, such as ball grid arrays and quad flat packs. A surface mount package is positioned directly beneath a modular optical transceiver. The surface mount package provides for electrically coupling external signals to the optical transceiver, so as to allow full performance functionality of data transfer components. An electrical coupling mechanism with high performance at high frequency is positioned between the surface mount package and the optical transceiver, electrically connecting them. In one implementation, the optical transceiver module is mounted directly to said surface mount package such that it is removable. In one embodiment, heat dissipation is provided by integral components and thermal vias, in addition to heat sinks. The apparatus, in one embodiment, allows optical transceivers to be modular and changeable, without connectors which can degrade high frequency signal transfer.
摘要翻译：一种装置和方法集成了用于在光学和电子介质之间传输信号的光学收发器与诸如球栅阵列和四方扁平封装的表面贴装封装。表面贴装封装位于模块化光收发器的正下方。表面安装封装提供了将外部信号电耦合到光收发器，以便允许数据传输组件的全面性能功能。在高频率下具有高性能的电耦合机构位于表面安装封装和光收发器之间，将它们电连接。在一个实现中，光收发器模块直接安装到所述表面安装封装，使得其可移除。在一个实施例中，除了散热器之外，散热由整体部件和热通孔提供。在一个实施例中，该装置允许光收发器是模块化和可变的，而不会降低高频信号传输的连接器。

2. 发明授权

US06734504B1 Method of providing HBM protection with a decoupled HBM structure 有权
标题翻译：提供具有解耦HBM结构的HBM保护的方法
公开(公告)号：US06734504B1
公开(公告)日：2004-05-11
申请号：US10117428
申请日：2002-04-05
申请人： James H. Lie , Yue Chen
发明人： James H. Lie , Yue Chen
IPC分类号： H01L2362
CPC分类号： H01L24/73 , H01L23/60 , H01L24/48 , H01L2224/05599 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48137 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device that includes an integrated circuit and an HBM structure formed on different semiconductor substrates is provided. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit and protection structures coupled to the input or output or input/output circuitry. In an embodiment, the integrated circuit may include input or output or input/output structures spaced across an area of the integrated circuit. The input or output or input/output circuitry of the HBM structure may be coupled to the input or output or input/output structures of the integrated circuit. A method for developing a design for an HBM structure is also provided. The method may include coupling an HBM structure formed on a first semiconductor substrate to an integrated circuit formed on a second semiconductor substrate. The method may also include testing the HBM structure and altering the HBM design based on the testing.
摘要翻译：提供了一种包括集成电路和形成在不同半导体衬底上的HBM结构的半导体器件。 HBM结构可以包括耦合到集成电路的输入或输出或输入/输出电路以及耦合到输入或输出或输入/输出电路的保护结构。在一个实施例中，集成电路可以包括在集成电路的一个区域上间隔开的输入或输出或输入/输出结构。 HBM结构的输入或输出或输入/输出电路可以耦合到集成电路的输入或输出或输入/输出结构。还提供了一种开发HBM结构设计的方法。该方法可以包括将形成在第一半导体衬底上的HBM结构耦合到形成在第二半导体衬底上的集成电路。该方法还可以包括测试HBM结构和基于测试改变HBM设计。

3. 发明授权

US06880145B1 Method for determining die placement based on global routing architecture 有权
标题翻译：基于全局路由架构确定芯片布局的方法
公开(公告)号：US06880145B1
公开(公告)日：2005-04-12
申请号：US10029089
申请日：2001-12-21
申请人： Andrew J. Wright , James H. Lie
发明人： Andrew J. Wright , James H. Lie
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method for interconnecting a plurality of dies. The method generally includes receiving a plurality of interconnect requirements for the dies. The interconnect requirements may include a priority for each of a plurality of nets. A position and an angle for one of the dies relative to a substrate may be calculated in response to the interconnect requirements. A plurality of nets may then be routed among the dies and a plurality of substrate pads defining external connections for the substrate. The dies may be mounted to the substrate after routing has been finalized.
摘要翻译：一种用于互连多个管芯的方法。该方法通常包括接收针对模具的多个互连要求。互连要求可以包括多个网络中的每一个的优先级。可以根据互连要求计算相对于基板的一个管芯的位置和角度。然后可以在管芯之间布置多个网，以及限定用于衬底的外部连接的多个衬底焊盘。路由完成之后，模具可以安装到基板上。

4. 发明授权

US06683468B1 Method and apparatus for coupling to a device packaged using a ball grid array 有权
标题翻译：用于耦合到使用球栅阵列封装的器件的方法和装置
公开(公告)号：US06683468B1
公开(公告)日：2004-01-27
申请号：US09942436
申请日：2001-08-29
申请人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
发明人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
IPC分类号： G01R3102
CPC分类号： G01R31/2884 , H01L23/49816 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2924/15311 , H01L2924/3011 , H05K1/0268 , H05K3/243 , H05K3/28 , H01L2924/00014
摘要： A ball grid array (BGA) package is disclosed. An interconnect structure is formed on a substrate that electrically connects the electrical device to be housed in the BGA package to the solder balls thereon. Contact pads are formed over the top surface of the substrate. These contact pads electrically connect to the interconnect structure. A layer of solder mask is formed over the substrate that includes openings that overlie the contact pads. The BGA is then completed using conventional process steps. Thereby, a BGA package is formed that includes contact pads disposed such that the contact pads are accessible from the top of the BGA package, making these contact pads easily accessible. Thus, when the BGA is attached to a circuit board, connection to circuits of the electrical device is obtainable.
摘要翻译：公开了一种球栅阵列（BGA）封装。在将要容纳在BGA封装中的电气装置电连接到其上的焊球的基板上形成互连结构。接触垫形成在衬底的顶表面上。这些接触垫电连接到互连结构。在衬底上形成一层焊料掩模，该层包括覆盖接触焊盘的开口。然后使用常规工艺步骤完成BGA。由此，形成BGA封装，其包括布置成使得接触焊盘可从BGA封装的顶部接近的接触焊盘，使得这些接触焊盘容易接近。因此，当BGA附接到电路板时，可以获得与电气装置的电路的连接。

5. 发明授权

US06671868B1 Method of creating MCM pinouts 有权
标题翻译：创建MCM引脚排列的方法
公开(公告)号：US06671868B1
公开(公告)日：2003-12-30
申请号：US10005823
申请日：2001-12-03
申请人： James H. Lie
发明人： James H. Lie
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , H01L23/49811 , H01L2924/0002 , H01L2924/00
摘要： A method for creating pinouts for inter-die connections comprising the steps of filling a number of columns of a computer readable file with information about pads and balls of the inter-die connections, marking portions of the computer readable file indicating a correlation between the pads and the balls, and generating a netlist according to one or more sets of computer executable instructions in the computer readable file.
摘要翻译：一种用于创建用于管芯间连接的引脚排列的方法，包括以下步骤：用关于管芯间连接的焊盘和球的信息填充计算机可读文件的多列，标记计算机可读文件的指示焊垫之间的相关性的部分和球，并且根据计算机可读文件中的一组或多组计算机可执行指令生成网表。

6. 发明授权

US07010772B1 Method and apparatus for generating superset pinout for devices with high-speed transceiver channels 失效
标题翻译：用于产生具有高速收发器通道的器件的超集管引脚分布的方法和装置
公开(公告)号：US07010772B1
公开(公告)日：2006-03-07
申请号：US09940749
申请日：2001-08-28
申请人： James H. Lie
发明人： James H. Lie
IPC分类号： G06F17/50 , G06F7/38
CPC分类号： G06F17/5068
摘要： A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the pinlist. Third, the superset pinout for the family of devices is created from said superset listing of pins to eliminate potential footprint variations within the family of devices. Fourth, each pin of the superset pinout associated with each member of the family of devices is marked.
摘要翻译：一种用于为一系列设备生成超集管引脚排列的方法。首先，针对系列设备中的每个设备定义了一个针对列表。第二，从引脚列表生成引脚的超集列表。第三，针对器件系列的超集管引脚排列由所述引脚的超集列表创建，以消除器件系列内的潜在的占位面积变化。第四，与设备系列的每个成员相关联的超集管引脚排列的每个引脚被标记。

7. 发明授权

US06649832B1 Apparatus and method for coupling with components in a surface mount package 有权
标题翻译：用于与表面安装封装中的部件耦合的装置和方法
公开(公告)号：US06649832B1
公开(公告)日：2003-11-18
申请号：US09944874
申请日：2001-08-31
申请人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
发明人： Brenor L. Brophy , James H. Lie , Andrew J. Wright
IPC分类号： H05K506
CPC分类号： H01L23/04 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12043 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/05599 , H01L2924/00
摘要： An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other electrical problems. An embodiment of the present invention also provides a method and apparatus that effectuates testing access, directly to the internal die component of the surface mount package or to a particular circuit node or conductive trace locale of the surface mount package, enabling performance evaluation and system debugging. Further, an embodiment of the present invention provides a method and apparatus that effectuates integration of surface mount package with an opto-electronic package. Further still, an embodiment of the present invention provides a method and apparatus that achieves these advantages with minimal cost.
摘要翻译：本发明的一个实施例提供一种方法和装置，其直接与内部管芯部件的单独构成子部件或表面安装封装的特定电路节点或导电迹线区域直接实现直接功能接口，而不会产生高频信号劣化或其他电气问题。本发明的一个实施例还提供了一种方法和装置，其实现了直接访问表面安装封装的内部管芯部件或表面安装封装的特定电路节点或导电迹线区域的测试访问，使得能够进行性能评估和系统调试。此外，本发明的实施例提供了一种实现表面贴装封装与光电封装集成的方法和装置。此外，本发明的一个实施例提供了以最小的成本实现这些优点的方法和装置。

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