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1. 发明申请

US20130171130A1 SOLUBLE INTERLEUKIN-20 RECEPTOR 审中-公开
标题翻译：可溶性INTERLEUKIN-20受体
公开(公告)号：US20130171130A1
公开(公告)日：2013-07-04
申请号：US13525466
申请日：2012-06-18
申请人： DONALD C. FOSTER , WENFENG XU , KAREN L. MADDEN , JAMES D. KELLY , CINDY A. SPRECHER , CAMERON S. BRANDT , MARK W. RIXON , SCOTT R. PRESNELL , BRIAN A. FOX
发明人： DONALD C. FOSTER , WENFENG XU , KAREN L. MADDEN , JAMES D. KELLY , CINDY A. SPRECHER , CAMERON S. BRANDT , MARK W. RIXON , SCOTT R. PRESNELL , BRIAN A. FOX
IPC分类号： C07K16/28
CPC分类号： C07K16/2866 , A61K38/00 , C07K14/7155 , C07K2319/00
摘要： A soluble receptor to IL-20 having two polypeptide subunits, IL-20RA (formerly called ZcytoR7) and IL-20RB (formerly called DIRS1). The two subunits are preferably linked together. In one embodiment one subunit is fused to the constant region of the light chain of an immunoglobulin, and the other subunit is fused to the constant region of the heavy chain of the immunoglobulin. The light chain and the heavy chain are connected via a disulfide bond.
摘要翻译：具有两个多肽亚单位IL-20RA（以前称为ZcytoR7）和IL-20RB（以前称为DIRS1）的IL-20的可溶性受体。两个亚基优选连接在一起。在一个实施方案中，一个亚基与免疫球蛋白的轻链的恒定区融合，另一个亚基与免疫球蛋白的重链的恒定区融合。轻链和重链通过二硫键连接。

2. 发明申请

US20100197575A1 SOLUBLE INTERLEUKIN-20 RECEPTOR 审中-公开
标题翻译：可溶性INTERLEUKIN-20受体
公开(公告)号：US20100197575A1
公开(公告)日：2010-08-05
申请号：US12509667
申请日：2009-07-27
申请人： Donald C. Foster , Wenfeng Xu , Karen L. Madden , James D. Kelly , Cindy A. Sprecher , Cameron S. Brandt , Mark W. Rixon , Scott R. Presnell , Brian A. Fox
发明人： Donald C. Foster , Wenfeng Xu , Karen L. Madden , James D. Kelly , Cindy A. Sprecher , Cameron S. Brandt , Mark W. Rixon , Scott R. Presnell , Brian A. Fox
IPC分类号： A61K38/17 , A61P37/06
CPC分类号： C07K16/2866 , A61K38/00 , C07K14/7155 , C07K2319/00
摘要： A soluble receptor to IL-20 having two polypeptide subunits, IL-20RA (formerly called ZcytoR7) and IL-20RB (formerly called DIRS1). The two subunits are preferably linked together. In one embodiment one subunit is fused to the constant region of the light chain of an immunoglobulin, and the other subunit is fused to the constant region of the heavy chain of the immunoglobulin. The light chain and the heavy chain are connected via a disulfide bond.
摘要翻译：具有两个多肽亚单位IL-20RA（以前称为ZcytoR7）和IL-20RB（以前称为DIRS1）的IL-20的可溶性受体。两个亚基优选连接在一起。在一个实施方案中，一个亚基与免疫球蛋白的轻链的恒定区融合，另一个亚基与免疫球蛋白的重链的恒定区融合。轻链和重链通过二硫键连接。

3. 发明申请

US20090203287A1 Sax-a-feed aka handy dandy bottle holder 审中-公开
标题翻译： Sax-a-feed又名方便的花瓶瓶
公开(公告)号：US20090203287A1
公开(公告)日：2009-08-13
申请号：US12220802
申请日：2009-01-05
申请人： James D. Kelly
发明人： James D. Kelly
IPC分类号： A63H33/00 , B65D23/12
CPC分类号： A61J15/0011 , A61J9/006 , A61J9/0607
摘要： The invention was made with a dual purpose, 1) a child's musical toy, and 2) a hands free baby bottle holder for feeding.
摘要翻译：本发明是用双重目的，1）一个孩子的音乐玩具，和2）一个免提婴儿奶瓶的饲养。

4. 发明授权

US07296174B2 Apparatus and method to interface two different clock domains 失效
标题翻译：接口两个不同时钟域的设备和方法
公开(公告)号：US07296174B2
公开(公告)日：2007-11-13
申请号：US10822534
申请日：2004-04-12
申请人： James D. Kelly
发明人： James D. Kelly
IPC分类号： G06F1/00 , G06F1/04 , G06F3/00
CPC分类号： G06F5/06
摘要： A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.
摘要翻译：齿轮箱放置在两个时钟域之间，以允许数据从一个域传输到另一个域。尽管两个域可以在相同的时钟频率下工作，但通常一个域具有比另一个更快的时钟速度。齿轮箱设置在两个时钟域之间，以通过选择识别数据何时使传输透明的模式来控制数据从一个到另一个的数据传输的定时。齿轮箱允许选择多个时钟比，使得两个域之间的特定时钟比可以容易地在用于数据传输的变速箱中选择。

5. 发明授权

US07206110B2 Memory cell dual protection 有权
标题翻译：存储单元双重保护
公开(公告)号：US07206110B2
公开(公告)日：2007-04-17
申请号：US11004595
申请日：2004-12-03
申请人： James D. Kelly , Shoucheng Zhang
发明人： James D. Kelly , Shoucheng Zhang
IPC分类号： G02B26/00 , G02F1/03
CPC分类号： G02B26/0841 , B81B7/0029 , B81B2201/047
摘要： A spatial light modulator for use in projection display applications is provided. The spatial light modulator includes a substrate including a plurality of electrically active circuits and an electrode layer electrically coupled to at least one of the plurality of electrically active circuits. In one embodiment, the electrode layer includes a semi-continuous layer with at least one optical path. The spatial light modulator also includes a shielding layer electrically isolated from the electrode layer and disposed between the substrate and the plurality of electrically active circuits and an electrical connector coupling the shielding layer to a reference potential. In a specific embodiment, the shielding layer of the spatial light modulator converts incident light energy to electrical current and routes the current back to a source. In another specific embodiment, the shielding layer converts electrical field disturbance to electrical current and routes the current back to a source.
摘要翻译：提供了用于投影显示应用的空间光调制器。该空间光调制器包括一个衬底，该衬底包括多个电活动电路和电耦合到多个电活动电路中的至少一个的电极层。在一个实施例中，电极层包括具有至少一个光路的半连续层。空间光调制器还包括与电极层电绝缘并且设置在基板和多个电活动电路之间的屏蔽层和将屏蔽层耦合到参考电位的电连接器。在具体实施例中，空间光调制器的屏蔽层将入射光能转换成电流并将电流路由回到源。在另一具体实施例中，屏蔽层将电场扰动转换成电流并将电流路由回到源。

6. 发明授权

US07117292B2 Apparatus and method to switch a FIFO between strobe sources 失效
标题翻译：在频闪源之间切换FIFO的装置和方法
公开(公告)号：US07117292B2
公开(公告)日：2006-10-03
申请号：US10822394
申请日：2004-04-12
申请人： James D. Kelly
发明人： James D. Kelly
IPC分类号： G11C7/22 , G06F1/04
CPC分类号： G06F5/06 , G06F5/10 , G06F12/0802
摘要： A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.
摘要翻译：先进先出（FIFO）单元在频闪源之间切换。 FIFO使用多路复用器在两个或更多个选通之间切换，以便不同的数据选通可以与FIFO一起使用以在数据中选通。在一个实现中，FIFO使用四个数据锁存器来选择数据位，并且每半个时钟周期将一对数据位输出到内部总线上。

7. 发明授权

US06941440B2 Addressing scheme supporting variable local addressing and variable global addressing 有权
公开(公告)号：US06941440B2
公开(公告)日：2005-09-06
申请号：US10439297
申请日：2003-05-15
申请人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
发明人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
IPC分类号： G06F3/00 , G06F9/42 , G06F12/00 , G06F12/08
CPC分类号： G06F13/1684
摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

8. 发明授权

US06336166B1 Memory control device with split read for ROM access 失效
标题翻译：存储器控制器，具有分离读取，用于ROM访问
公开(公告)号：US06336166B1
公开(公告)日：2002-01-01
申请号：US08834922
申请日：1997-04-07
申请人： James D. Kelly
发明人： James D. Kelly
IPC分类号： G06F1200
CPC分类号： G06F12/0638
摘要： In a computer memory system, memory access operations are significantly enhanced by employing a data path between the read only memory (ROM) and the system processor that is separate and independent from the data path or paths between the system processor and the random access memory (i.e., RAM or DRAM). The separate ROM data path includes a full cache line buffer which stores the ROM data until the system data bus is available to transport the ROM data. With a separate ROM data path, that includes a full cache line buffer, memory access operations are more efficiently conducted because a RAM access (i.e., a read or write operation) and a ROM access (i.e., a read operation) can be executed concurrently.
摘要翻译：在计算机存储器系统中，通过在只读存储器（ROM）和与数据路径分开独立的系统处理器之间的数据路径或系统处理器与随机存取存储器之间的路径即RAM或DRAM）。单独的ROM数据路径包括完整的高速缓存行缓冲器，其存储ROM数据，直到系统数据总线可用于传送ROM数据。通过单独的ROM数据路径，其包括完整的高速缓存行缓冲器，由于可以同时执行RAM访问（即，读取或写入操作）和ROM访问（即，读取操作），因此更有效地执行存储器访问操作。

9. 发明授权

US5802055A Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads 失效
标题翻译：用于流水线读取的总线桥中的动态缓冲器分配的方法和装置
公开(公告)号：US5802055A
公开(公告)日：1998-09-01
申请号：US635646
申请日：1996-04-22
申请人： William Todd Krein , Charles M. Flaig , James D. Kelly
发明人： William Todd Krein , Charles M. Flaig , James D. Kelly
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.
摘要翻译：总线桥接电路采用动态分配方案，允许读取事务被流水线化而不会出现死锁，而不需要为读取响应事务永久保留多个缓冲区。总线桥接电路将输入和输出缓冲器与节点相关联，并且包括状态机来监视当前在构成缓冲器的时隙中的事务包的数量和类型。特别地，状态机监视加载在输出缓冲器槽中的事务数据包的数量，节点的未完成读取事务的数量以及当前加载在输出缓冲器中的读取响应事务的数量。状态机然后允许节点加载READ或WRITE事务，只有当监视的数据指示至少一个缓冲区槽可用于服务节点随后加载的READ RESPONSE。只有当未分配的缓冲槽可用于服务相应的READ RESPONSE时，状态机才会向节点启动READ。

10. 发明授权

US5474982A PDGF analogs and methods of use 失效
公开(公告)号：US5474982A
公开(公告)日：1995-12-12
申请号：US273779
申请日：1994-07-12
申请人： Mark J. Murray , James D. Kelly
发明人： Mark J. Murray , James D. Kelly
IPC分类号： A61K38/00 , C07K14/15 , C07K14/49 , C12N15/81
CPC分类号： C12N15/81 , C07K14/49 , A61K38/00 , C07K2319/02 , C07K2319/036 , C07K2319/75 , Y10S514/97
摘要： Proteins having substantially the same biological activity as PDGF are provided. In one aspect, a protein homodimer having two polypeptide chains is disclosed, each of the chains being a mosaic of amino acid sequences substantially identical to portions of the A- and B-chains of PDGF, the protein being chemotactic or mitogenic for fibroblasts. Therapeutic compositions comprising such proteins in combination with a physiologically acceptable carrier or diluent are also provided. Such therapeutic compositions may be used within methods for enhancing the wound-healing process in warm-blooded animals.

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