会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Thermal shutdown circuit using a pair of scaled transistors
    • 热关断电路使用一对定标晶体管
    • US5737170A
    • 1998-04-07
    • US313480
    • 1994-09-27
    • James C. Moyer
    • James C. Moyer
    • H02H5/04
    • H02H5/044
    • The base of a thermal shutdown bipolar transistor having a V.sub.BE(on) which decreases with increasing temperature is biased with a bias voltage V.sub.PTATbias which increases proportionally with increasing absolute temperature. By supplying the base of the thermal shutdown transistor with a bias voltage V.sub.PTATbias which increases with increasing temperature rather than a bias voltage that remains constant or decreases with increasing temperature, the temperature at which the thermal shutdown transistor turns on is made more predictable and the thermal shutdown transistor is made to turn on more sharply at a desired thermal shutdown temperature. The bias voltage V.sub.PTATbias may be generated by driving a current which increases proportionally with increasing absolute temperature across a resistor. Current sources employing feedback control loops are disclosed for generating such a current. Startup current sources are disclosed for starting control loop operation. A hysteresis circuit is disclosed which causes the thermal shutdown transistor to turn on at a relatively high temperature and to turn off at a relatively low temperature.
    • 具有随着温度升高而降低的VBE(on)的热关断双极晶体管的基极利用随着绝对温度的升高而成比例地增加的偏置电压VPTATbias而偏置。 通过向热关断晶体管的基极提供具有随着温度升高而增加的偏置电压VPTATbias,而不是随着温度升高而保持恒定或降低的偏置电压,使热关断晶体管导通的温度变得更可预测,并且热 使关断晶体管在所需的热关断温度下更快地导通。 偏置电压VPTATbias可以通过驱动与跨越电阻器的绝对温度上升成比例地增加的电流来产生。 公开了采用反馈控制回路的电流源来产生这样的电流。 公开启动电流源用于启动控制环操作。 公开了一种滞后电路,其导致热关断晶体管在相对较高的温度下导通,并在相对较低的温度下关断。
    • 8. 发明授权
    • Bipolar transistor structure using ballast resistor
    • 使用镇流电阻的双极晶体管结构
    • US5374844A
    • 1994-12-20
    • US197658
    • 1994-02-17
    • James C. Moyer
    • James C. Moyer
    • H01L21/331H01L29/08H01L29/73H01L29/72
    • H01L29/66303H01L29/0813H01L29/7304
    • A transistor structure incorporates a polysilicon layer which is doped with N-type dopants and is used as an emitter ballast resistor in an array of NPN transistors. In one embodiment, the polysilicon layer is also used as a diffusion source to form N-type emitter regions within a deep and high resistivity P-well, which acts as a relatively high value base ballast resistor for the transistor. In another embodiment, a standard base is used, contributing little base ballast resistance. A buried collector region carries collector current. Preferably, the emitter regions are formed as oblong strips. P-type base contact regions, also generally formed as oblong strips, are formed in the surface of this P-well parallel to the emitter regions. The dimensions of the base contact regions may be varied in order to achieve a constant base-emitter voltage along the entire length of each emitter strip. An emitter metal layer overlies the polysilicon layer and contacts the polysilicon layer through openings in an insulating layer. The resulting three dimensional structure in one embodiment thus incorporates a stacked collector region, base ballast resistor, base region, emitter regions, emitter ballast resistors, and emitter metal layer. In another embodiment, the same three dimensional structure results except that there is no base ballast resistor. Dimensions of the emitter metal layer and other metal layers may be adjusted so that the transistor structure has a trapezoidal shape and requires less silicon real estate.
    • 晶体管结构包含掺杂有N型掺杂剂的多晶硅层,并用作NPN晶体管阵列中的发射极镇流电阻器。 在一个实施例中,多晶硅层也用作扩散源,以在深和高电阻率P阱内形成N型发射极区,其作为晶体管的相对高的基极镇流电阻。 在另一个实施方案中,使用标准碱,贡献很小的抗基质耐压性。 埋地集电极区域携带集电极电流。 优选地,发射极区域形成为长方形条。 通常形成为长方形的P型基极接触区域形成在平行于发射极区域的该P阱的表面中。 可以改变基极接触区域的尺寸,以便沿着每个发射极条的整个长度实现恒定的基极 - 发射极电压。 发射极金属层覆盖多晶硅层,并通过绝缘层中的开口与多晶硅层接触。 因此,在一个实施例中得到的三维结构包括堆叠的集电极区域,基极镇流电阻器,基极区域,发射极区域,发射极镇流电阻器和发射极金属层。 在另一个实施例中,除了没有基极镇流电阻之外,具有相同的三维结构结果。 可以调节发射极金属层和其它金属层的尺寸,使得晶体管结构具有梯形形状并且需要较少的硅的不动产。