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1. 发明授权

US5434814A Circuit for repairing defective read only memories with redundant NAND string 失效
标题翻译：用冗余NAND串修复有缺陷的只读存储器的电路
公开(公告)号：US5434814A
公开(公告)日：1995-07-18
申请号：US132175
申请日：1993-10-06
申请人： Sung-Hee Cho , Kang-Deog Suh , Hyong-Gon Lee , Jae-Yeong Do
发明人： Sung-Hee Cho , Kang-Deog Suh , Hyong-Gon Lee , Jae-Yeong Do
IPC分类号： G11C17/00 , G11C17/18 , G11C29/00 , G11C29/04 , H01L27/00 , G11C11/40
CPC分类号： G11C29/822
摘要： A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.
摘要翻译：具有缺陷修复功能的掩模ROM存储对应于缺陷存储单元的地址信号，然后根据存储的地址信号是否与外部提供的地址信号相同，选择性地激活冗余行解码器或行解码器。掩模ROM包括通过在字线方向上分组以行和列排列的多个只读存储器单元形成的第一和第二存储单元阵列; 第一和第二行解码器，用于组合外部提供的行地址信号，以选择性地驱动第一和第二存储单元阵列的字线; 以及行解码器选择器，用于根据包括第一存储单元阵列的缺陷存储单元的行块存储其中的地址信号，以便在外部行地址信号等于第一行解码器时使第一行解码器失活，并激活第二行解码器存储在行解码器选择器中的地址信号。

2. 发明授权

US5285409A Serial input/output memory with a high speed test device 失效
标题翻译：具有高速测试装置的串行输入/输出存储器
公开(公告)号：US5285409A
公开(公告)日：1994-02-08
申请号：US871733
申请日：1992-04-21
申请人： Jun-sik Hwangbo , Jae-Yeong Do
发明人： Jun-sik Hwangbo , Jae-Yeong Do
IPC分类号： G01R31/317 , G06F11/22 , G11C7/00 , G11C8/00
CPC分类号： G01R31/31701 , G06F11/2273 , G06F2201/88
摘要： A device for changing a frequency of an internal control clock for testing a chip, by incorporating a mode selection circuit (30) and a high voltage detection circuit (40) in a serial input/output memory. The mode selection circuit (30) is connected between two selected adjacent circuits C.sub.n-2, C.sub.n-1 among a plurality of frequency conversion circuits C.sub.1 . . . C.sub.n, for accessing selectively either a clock pulse CP.sub.n-2 from the frequency conversion circuit C.sub.n-2, arranged in front thereof or a system clock XSK, in dependence upon an internal voltage sense signal IV, IVB. The high voltage detection circuit (40) transmits the internal voltage sense signal to the mode selection circuit (30) by detecting a level of externally applied voltage XV. The internal control clock ICK provided by this device attains a period of T.sub.XSK .times.2.sup.n-M+1, wherein "M" is a number of the counter receiving the mode selection signals MS, MSB next to the mode selection circuit.
摘要翻译：一种用于通过在串行输入/输出存储器中并入模式选择电路（30）和高电压检测电路（40）来改变用于测试芯片的内部控制时钟的频率的装置。模式选择电路（30）连接在多个频率转换电路C1中的两个选定的相邻电路Cn-2，Cn-1之间。。。 Cn，用于根据内部电压检测信号IV，IVB选择性地存取频率转换电路Cn-2的时钟脉冲CPn-2或其系统时钟XSK。高电压检测电路（40）通过检测外部施加的电压XV的电平将内部电压检测信号发送到模式选择电路（30）。由该装置提供的内部控制时钟ICK达到TXSK * 2n-M + 1的周期，其中“M”是接收模式选择电路旁边的模式选择信号MS，MSB的计数器的数目。

3. 发明授权

US4794568A Redundancy circuit for use in a semiconductor memory device 失效
标题翻译：用于半导体存储器件的冗余电路
公开(公告)号：US4794568A
公开(公告)日：1988-12-27
申请号：US44702
申请日：1987-05-01
申请人： Hyung-Kyu Lim , Jae-Yeong Do , Rustam Mehta
发明人： Hyung-Kyu Lim , Jae-Yeong Do , Rustam Mehta
IPC分类号： H01L27/10 , G11C11/401 , G11C29/00 , G11C29/04 , H01L27/00 , G11C7/00
CPC分类号： G11C29/785
摘要： A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.
摘要翻译：正常解码器和具有地址程序设备的冗余解码器用于替换坏小区。地址编程设备的数量比用于选择正常行或列的输入地址位数多一个。附加程序设备的输入信号与其他程序设备之一的输入信号互补。程序设备的程序有两个步骤来修复故障单元。为了提高冗余的可靠性，在程序设备中使用的非易失性存储元件是连接四个单元FLOTOX型非易失性存储器件的桥。

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