专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160098509A1 INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT 有权
标题翻译：集成电路和集成电路布局的设计方法
公开(公告)号：US20160098509A1
公开(公告)日：2016-04-07
申请号：US14868745
申请日：2015-09-29
申请人： JAE-WOO SEO , HA-YOUNG KIM , HYUN-JEONG ROH
发明人： JAE-WOO SEO , HA-YOUNG KIM , HYUN-JEONG ROH
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/70 , G03F7/70466 , G06F17/50 , G06F17/5068 , G06F2217/12 , H01L21/31144
摘要： A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
摘要翻译：设计集成电路（IC）的布局的方法包括将第一单元放置在布局中，在第一和第二单元之间的第一边界处将第二单元放置在与第一单元相邻的布局中，并且产生多个命令可由处理器执行，以形成基于布局的半导体器件。第一单元包括第一图案和第二图案。第一图案和第二图案与第一边界相邻，第一图案和第二图案具有不同的颜色，并且第一图案和第一边界之间的第一边界空间不同于第二图案和第一边界之间的第二边界空间。

2. 发明申请

US20120242190A1 SAW SENSOR 审中-公开
标题翻译： SAW传感器
公开(公告)号：US20120242190A1
公开(公告)日：2012-09-27
申请号：US12672686
申请日：2008-08-08
申请人： Du-Hwan Choi , Tae-Ho Kim , Jae-Woo Seo , Seung-Man Lim , Do-Hyung Kim , Byeong-Kyoo Shon
发明人： Du-Hwan Choi , Tae-Ho Kim , Jae-Woo Seo , Seung-Man Lim , Do-Hyung Kim , Byeong-Kyoo Shon
IPC分类号： G01L1/16
CPC分类号： G01L9/0025 , G01L9/008 , G01L19/0092
摘要： Provided is a surface acoustic wave (SAW) sensor sensing pressure, temperature, etc., by using a SAW. The SAW sensor includes: a substrate having one of its surfaces formed with a cavity having a predetermined depth; a piezoelectric plate which has piezoelectricity, so as to make a SAW, and which is adhered to the surface in which the cavity is formed, so as to cover the cavity of the substrate; a pressure resonator which is installed to a portion of the piezoelectric plate that corresponds to the cavity groove, and which generates a SAW due to a radio frequency (RF) signal applied thereto; and a reference resonator which is installed to the piezoelectric plate to be outside the portion corresponding to the cavity and be parallel to the pressure resonator, and which generates a SAW due to the RF signal applied thereto.
摘要翻译：提供了通过使用SAW来感测压力，温度等的表面声波（SAW）传感器。 SAW传感器包括：基板，其表面中的一个形成有具有预定深度的空腔; 压电板，其具有压电性，以制造SAW，并且粘附到形成有空腔的表面，以覆盖基板的空腔; 压电谐振器，其被安装到压电板的对应于空腔凹槽的部分，并且由施加到其上的射频（RF）信号产生SAW; 以及参考谐振器，其被安装到压电板上以在与腔相对应的部分的外侧并且平行于压力谐振器，并且由于施加到其上的RF信号而产生SAW。

3. 发明申请

US20150014775A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150014775A1
公开(公告)日：2015-01-15
申请号：US14273789
申请日：2014-05-09
申请人： Jae-Woo SEO , Gun-Ok JUNG , Min-Su KIM , Sang-Shin HAN , Ju-Hyun KANG , Uk-Rae CHO
发明人： Jae-Woo SEO , Gun-Ok JUNG , Min-Su KIM , Sang-Shin HAN , Ju-Hyun KANG , Uk-Rae CHO
IPC分类号： H01L29/78 , H01L27/06 , H01L23/538 , H01L27/092
CPC分类号： H01L29/785 , H01L23/5286 , H01L23/538 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L27/0207 , H01L27/0629 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15331 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括：第一源电极，被配置为将第一电力轨连接到第一杂质区，第一电源轨耦合到第一电压源;第二源极，被配置为将第二电力轨连接到第二杂质区; 第二电源轨耦合到第二电压源，第一和第二电压源不同，第一和第二杂质区上的栅电极，第一杂质区上的第一漏电极，第二杂质区上的第二漏电极，连接到所述第一漏电极和所述第二漏极的互连线，所述互连线形成至少一个闭环。

4. 发明授权

US08869089B2 Semiconductor integrated circuit and method of designing the same 有权
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US08869089B2
公开(公告)日：2014-10-21
申请号：US13708066
申请日：2012-12-07
申请人： Sang-hoon Baek , Jae-woo Seo
发明人： Sang-hoon Baek , Jae-woo Seo
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices.
摘要翻译：根据发明构思的示例性实施例，一种设计半导体集成电路的方法包括：创建标记层，其指示要在宽度，高度和/或宽度中的至少一个中改变的多个半导体器件中的至少一个半导体器件其相邻半导体器件的空间; 以及将所述标记层应用于先前创建的布局以生成在与相邻半导体器件的宽度，高度和空间中的至少一个中改变的所述至少一个半导体器件的新库。标记层可以基于多个半导体器件中的至少一个半导体器件的特性变化。

5. 发明申请

US20130263077A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME 有权
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20130263077A1
公开(公告)日：2013-10-03
申请号：US13708066
申请日：2012-12-07
申请人： Sang-hoon BAEK , Jae-woo SEO
发明人： Sang-hoon BAEK , Jae-woo SEO
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices.
摘要翻译：根据发明构思的示例性实施例，一种设计半导体集成电路的方法包括：创建标记层，其指示要在宽度，高度和/或宽度中的至少一个中改变的多个半导体器件中的至少一个半导体器件其相邻半导体器件的空间; 以及将所述标记层应用于先前创建的布局以生成在与相邻半导体器件的宽度，高度和空间中的至少一个中改变的所述至少一个半导体器件的新库。标记层可以基于多个半导体器件中的至少一个半导体器件的特性变化。

6. 发明授权

US09934347B2 Integrated circuit and method of designing layout of integrated circuit 有权
公开(公告)号：US09934347B2
公开(公告)日：2018-04-03
申请号：US14868745
申请日：2015-09-29
申请人： Jae-Woo Seo , Ha-Young Kim , Hyun-Jeong Roh
发明人： Jae-Woo Seo , Ha-Young Kim , Hyun-Jeong Roh
IPC分类号： G06F17/50 , G03F1/70 , H01L21/311 , G03F7/20
CPC分类号： G06F17/5072 , G03F1/70 , G03F7/70466 , G06F17/50 , G06F17/5068 , G06F2217/12 , H01L21/31144
摘要： A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

7. 发明申请

US20160300766A1 METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：用于设计半导体器件的布局的方法和使用其制造半导体器件的方法
公开(公告)号：US20160300766A1
公开(公告)日：2016-10-13
申请号：US15094764
申请日：2016-04-08
申请人： Ha-Young KIM , JinTae KIM , Jae-Woo SEO , Dong-yeon HEO
发明人： Ha-Young KIM , JinTae KIM , Jae-Woo SEO , Dong-yeon HEO
IPC分类号： H01L21/8234 , H01L27/06 , H01L21/768 , G06F17/50
CPC分类号： H01L21/823475 , G06F17/5072 , G06F17/5081 , H01L21/76816 , H01L21/76892 , H01L21/823871 , H01L27/0207 , H01L27/0629
摘要： A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.
摘要翻译：一种制造半导体器件的方法包括提供用于形成彼此相邻的第一逻辑单元和第二逻辑单元的预导线和后导线，以及相邻的虚拟单元和第三逻辑单元对彼此。与第二逻辑单元相邻的第一导线从第一逻辑单元的导线之间隔开第二参考距离，与第二逻辑单元相邻的第二导线相隔离第二逻辑单元的导线之间。与第三逻辑单元相邻的虚拟线从虚拟单元的导线之间隔开第二基准距离，该第二基准距离与第三逻辑导线之间的与虚设单元相邻的第三导线细胞。第二参考距离大于第一参考距离。

8. 发明申请

US20160300840A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE SAME 有权
标题翻译：制造半导体器件的方法及其制造的半导体器件
公开(公告)号：US20160300840A1
公开(公告)日：2016-10-13
申请号：US15094280
申请日：2016-04-08
申请人： Jae-Woo SEO , Jaeha LEE
发明人： Jae-Woo SEO , Jaeha LEE
IPC分类号： H01L27/092 , G06F17/50 , H01L23/528 , H01L27/02 , H01L21/8238 , H01L21/768
CPC分类号： G06F17/5077 , G06F17/5072 , G06F17/5081 , H01L21/76816 , H01L21/76892 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/528 , H01L27/0207
摘要： A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.
摘要翻译：提供一种制造半导体器件的方法。该方法包括布置用于形成第一和第二单元的预导线和导电线。第一和第二单元在第一方向上彼此相邻。第一单元的第一导电线在垂直于第一方向的第二方向上延伸并且与第一和第二单元之间的边界相邻。第二单元的第二导线和第三导线在第一方向上延伸并且与边界相邻。第二和第三导线分别设置在沿着第一方向延伸的多个轨道中的两个不相邻的轨道上。第一导线与两个不相邻的轨道中的一个相交，一个轨道设置在两个不相邻的轨道之间。

9. 发明申请

US20150244366A1 INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：集成电路和半导体器件，包括它们
公开(公告)号：US20150244366A1
公开(公告)日：2015-08-27
申请号：US14624646
申请日：2015-02-18
申请人： DAL-HEE LEE , Jae-Woo Seo , Min-Ho Park
发明人： DAL-HEE LEE , Jae-Woo Seo , Min-Ho Park
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0944 , G06F17/50
CPC分类号： H03K19/0013 , G06F17/5072 , H03K19/018507 , H03K19/018521 , H03K19/0944
摘要： An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.
摘要翻译：集成电路（IC）包括至少一个单元电池。所述至少一个单元单元包括被配置为处理第一位信号的第一位电路，被配置为处理第二位信号的第二位电路，与所述至少一个单位单元的边界间隔开的第一阱，并被偏置到第一位电压，第二阱偏压到不同于第一电压的第二电压。第一和第二位电路中的每一个包括设置在第一阱中的多个晶体管中的至少一个晶体管。

10. 发明授权

US09571076B2 Bidirectional delay circuit and integrated circuit including the same 有权
标题翻译：双向延迟电路和集成电路包括相同
公开(公告)号：US09571076B2
公开(公告)日：2017-02-14
申请号：US14877258
申请日：2015-10-07
申请人： Jae-Woo Seo , Sung-Hyun Park , Woo-Jin Rim , Ha-Young Kim , Jae-Ha Lee , Yong-Ho Kim
发明人： Jae-Woo Seo , Sung-Hyun Park , Woo-Jin Rim , Ha-Young Kim , Jae-Ha Lee , Yong-Ho Kim
IPC分类号： H03K17/284 , H03K5/12 , H03K17/687
CPC分类号： H03K5/12 , H03K5/13 , H03K17/687 , H03K2005/00215
摘要： A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.
摘要翻译：双向延迟电路包括输入驱动电路和延迟开关电路。输入驱动电路连接在输入节点和中间节点之间，并且输入驱动电路放大通过输入节点接收的输入信号，以通过中间节点生成中间信号。延迟开关电路连接在中间节点和延迟节点之间，并且延迟开关电路响应于门信号延迟中间信号的上升沿和下降沿，以通过延迟节点产生延迟信号。门信号可以响应于输入信号而转变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式