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1. 发明授权

US07902872B2 Data transmitters and methods thereof 有权
标题翻译：数据发射机及其方法
公开(公告)号：US07902872B2
公开(公告)日：2011-03-08
申请号：US11892434
申请日：2007-08-23
申请人： Ki-Hong Kim , Soo-Won Kim , Gil-Su Kim , Woo-Kwan Lee , Woo-Jin Rim
发明人： Ki-Hong Kim , Soo-Won Kim , Gil-Su Kim , Woo-Kwan Lee , Woo-Jin Rim
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.
摘要翻译：在数据发送器中，主线驱动电路经由信道将输入信号发送到接收器。预加重电路强调发送的输入信号的电压电平，并且预加重控制器控制预加重电路。预加重控制器根据信道的转换条件调整预加重电路的预加重电平，以增加在输入信号的转变时间处提供给信道的电流量。

2. 发明申请

US20080048720A1 Data transmitters and methods thereof 有权
标题翻译：数据发射机及其方法
公开(公告)号：US20080048720A1
公开(公告)日：2008-02-28
申请号：US11892434
申请日：2007-08-23
申请人： Ki-Hong Kim , Soo-Won Kim , Gil-Su Kim , Woo-Kwan Lee , Woo-Jin Rim
发明人： Ki-Hong Kim , Soo-Won Kim , Gil-Su Kim , Woo-Kwan Lee , Woo-Jin Rim
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.
摘要翻译：在数据发送器中，主线驱动电路经由信道将输入信号发送到接收器。预加重电路强调发送的输入信号的电压电平，并且预加重控制器控制预加重电路。预加重控制器根据信道的转换条件调整预加重电路的预加重电平，以增加在输入信号的转变时间处提供给信道的电流量。

3. 发明授权

US09571076B2 Bidirectional delay circuit and integrated circuit including the same 有权
标题翻译：双向延迟电路和集成电路包括相同
公开(公告)号：US09571076B2
公开(公告)日：2017-02-14
申请号：US14877258
申请日：2015-10-07
申请人： Jae-Woo Seo , Sung-Hyun Park , Woo-Jin Rim , Ha-Young Kim , Jae-Ha Lee , Yong-Ho Kim
发明人： Jae-Woo Seo , Sung-Hyun Park , Woo-Jin Rim , Ha-Young Kim , Jae-Ha Lee , Yong-Ho Kim
IPC分类号： H03K17/284 , H03K5/12 , H03K17/687
CPC分类号： H03K5/12 , H03K5/13 , H03K17/687 , H03K2005/00215
摘要： A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.
摘要翻译：双向延迟电路包括输入驱动电路和延迟开关电路。输入驱动电路连接在输入节点和中间节点之间，并且输入驱动电路放大通过输入节点接收的输入信号，以通过中间节点生成中间信号。延迟开关电路连接在中间节点和延迟节点之间，并且延迟开关电路响应于门信号延迟中间信号的上升沿和下降沿，以通过延迟节点产生延迟信号。门信号可以响应于输入信号而转变。

4. 发明申请

US20160105166A1 BIDIRECTIONAL DELAY CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：双向延迟电路和集成电路，包括它们
公开(公告)号：US20160105166A1
公开(公告)日：2016-04-14
申请号：US14877258
申请日：2015-10-07
申请人： JAE-WOO SEO , SUNG-HYUN PARK , WOO-JIN RIM , HA-YOUNG KIM , JAE-HA LEE , YONG-HO KIM
发明人： JAE-WOO SEO , SUNG-HYUN PARK , WOO-JIN RIM , HA-YOUNG KIM , JAE-HA LEE , YONG-HO KIM
IPC分类号： H03K5/12 , H03K17/687
CPC分类号： H03K5/12 , H03K5/13 , H03K17/687 , H03K2005/00215
摘要： A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.
摘要翻译：双向延迟电路包括输入驱动电路和延迟开关电路。输入驱动电路连接在输入节点和中间节点之间，并且输入驱动电路放大通过输入节点接收的输入信号，以通过中间节点生成中间信号。延迟开关电路连接在中间节点和延迟节点之间，并且延迟开关电路响应于门信号延迟中间信号的上升沿和下降沿，以通过延迟节点产生延迟信号。门信号可以响应于输入信号而转变。

5. 发明授权

US08416637B2 Semiconductor memory apparatus, and circuit and method for controlling faulty address therein 有权
标题翻译：半导体存储装置，以及用于控制其中的错误地址的电路和方法
公开(公告)号：US08416637B2
公开(公告)日：2013-04-09
申请号：US12836505
申请日：2010-07-14
申请人： Woo Jin Rim
发明人： Woo Jin Rim
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C13/0004 , G11C17/165 , G11C29/789
摘要： A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.
摘要翻译：错误的地址控制电路包括可变电阻熔丝单元，其被配置为响应于地址信号而被驱动，所述可变电阻熔丝单元的电阻值基于所施加电流的量来确定; 驱动单元，被配置为响应于故障地址控制信号，基于所述可变电阻熔丝单元的电阻值输出驱动信号; 以及地址存储和确定单元，被配置为接收地址信号，由驱动信号驱动以输出地址信号或地址信号的反相信号。

6. 发明申请

US20110058411A1 PHASE CHANGE MEMORY SYSTEM HAVING WRITE DRIVER 审中-公开
标题翻译：具有写入驱动器的相变存储器系统
公开(公告)号：US20110058411A1
公开(公告)日：2011-03-10
申请号：US12643490
申请日：2009-12-21
申请人： Woo Jin RIM
发明人： Woo Jin RIM
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory system capable of gradually reducing current at the time of writing set data by using a small number of control circuits while occupying a small dimension is disclosed. The phase change memory system includes a memory cell array including a plurality of memory cells, each including a phase change material which is changed into a set or reset state depending on the amount of current, and a write driver supplying current corresponding to a set or reset state to a selected memory cell of the memory cell array. The write driver includes a slow quenching unit including an analog circuit supplying current slowly decreased in the memory cell array.
摘要翻译：公开了一种能够在占用小尺寸的同时通过使用少量控制电路在写入设置数据时逐渐减小电流的相变存储器系统。相变存储器系统包括存储单元阵列，其包括多个存储单元，每个存储单元包括相变材料，该相变材料根据电流量而变为设定或复位状态;以及写入驱动器，复位状态到存储单元阵列的选定存储单元。写驱动器包括缓慢淬火单元，其包括提供存储单元阵列中缓慢减小的电流的模拟电路。

7. 发明授权

US07812658B2 Clock generation circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US07812658B2
公开(公告)日：2010-10-12
申请号：US12346814
申请日：2008-12-30
申请人： Woo-Jin Rim
发明人： Woo-Jin Rim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0805
摘要： A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation, tOS = 2 ⁢ ⁢ N × DD = 2 ⁢ ⁢ N × L × tCLK M where each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.
摘要翻译：一种时钟发生电路，其包括：包括串联连接的M个延迟单元的参考时钟延迟电路，并且被配置为将参考时钟延迟L个周期; 以及包括串联连接的N个延迟单元的振荡电路，并且被配置为根据以下等式生成振荡时钟：tOS = 2·n·N×DD = 2·秘诀N×L×tCLK M其中每个延迟单元被配置为将输入信号延迟参考延迟量DD，tOS是振荡时钟的周期，并且tCLK是参考时钟。

8. 发明申请

US20110157969A1 SEMICONDUCTOR MEMORY APPARATUS, AND CIRCUIT AND METHOD FOR CONTROLLING FAULTY ADDRESS THEREIN 有权
标题翻译：半导体存储器装置，以及用于控制故障地址的电路和方法
公开(公告)号：US20110157969A1
公开(公告)日：2011-06-30
申请号：US12836505
申请日：2010-07-14
申请人： Woo Jin RIM
发明人： Woo Jin RIM
IPC分类号： G11C11/00 , G11C29/00 , G11C17/16
CPC分类号： G11C17/16 , G11C13/0004 , G11C17/165 , G11C29/789
摘要： A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.
摘要翻译：错误的地址控制电路包括可变电阻熔丝单元，其被配置为响应于地址信号而被驱动，所述可变电阻熔丝单元的电阻值基于所施加电流的量来确定; 驱动单元，被配置为响应于故障地址控制信号，基于所述可变电阻熔丝单元的电阻值输出驱动信号; 以及地址存储和确定单元，被配置为接收地址信号，由驱动信号驱动以输出地址信号或地址信号的反相信号。

9. 发明申请

US20100052749A1 CLOCK GENERATION CIRCUIT 失效
标题翻译：时钟发生电路
公开(公告)号：US20100052749A1
公开(公告)日：2010-03-04
申请号：US12346814
申请日：2008-12-30
申请人： Woo-Jin RIM
发明人： Woo-Jin RIM
IPC分类号： H03L7/08
CPC分类号： H03L7/0812 , H03L7/0805
摘要： A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation, tOS = 2   N × DD = 2   N × L × tCLK M where each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.
摘要翻译：一种时钟发生电路，其包括：包括串联连接的M个延迟单元的参考时钟延迟电路，并且被配置为将参考时钟延迟L个周期; 以及包括串联连接的N个延迟单元的振荡电路，并且被配置为根据以下等式生成振荡时钟：tOS = 2÷N×DD = 2N×L×tCLK M其中每个延迟单元被配置为将输入信号延迟参考延迟量DD，tOS是振荡时钟的周期，并且tCLK是参考时钟。

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