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1. 发明授权

US06605508B2 Semiconductor device and method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06605508B2
公开(公告)日：2003-08-12
申请号：US10180650
申请日：2002-06-26
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L21336
CPC分类号： H01L27/0688 , H01L27/10858 , H01L27/10885 , H01L27/10888 , H01L27/1203 , H01L28/55
摘要： The disclosed semiconductor device includes a semiconductor substrate, a logic circuit area formed on the semiconductor substrate, the logic circuit area includes transistors for driving bit lines, and a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area. Also the disclosed method of fabricating the semiconductor device includes the steps of forming a logic circuit area on a semiconductor substrate, the logic circuit area includes interconnection wirings connected to transistors for driving bit lines, forming bit lines electrically connected to the interconnection wirings at the upper side thereof, forming a silicon film connected to the bit lines at the upper side thereof and defining a cell forming area, forming transistors on the silicon film, each transistor including a gate electrode, a source electrode, and a drain electrode, and forming capacitors electrically connected to the source electrodes at the upper side of the transistor.
摘要翻译：所公开的半导体器件包括半导体衬底，形成在半导体衬底上的逻辑电路区域，逻辑电路区域包括用于驱动位线的晶体管和层叠在逻辑电路区域上的铁电存储区域，并且包括晶体管区域和电容器区域。所公开的制造半导体器件的方法还包括在半导体衬底上形成逻辑电路区域的步骤，逻辑电路区域包括连接到用于驱动位线的晶体管的互连布线，形成与上部的互连布线电连接的位线在其上侧形成连接到位线的硅膜并限定电池形成区域，在硅膜上形成晶体管，每个晶体管包括栅电极，源电极和漏电极，以及形成电容器电连接到晶体管上侧的源电极。

2. 发明授权

US06483152B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06483152B1
公开(公告)日：2002-11-19
申请号：US09547003
申请日：2000-04-11
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L2978
CPC分类号： H01L21/8234 , H01L27/0629
摘要： A semiconductor device and a method of fabricating the same are disclosed. A resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction region are formed at both sides of the gate in the substrate. A dummy gate electrode over the resistor where a first insulating layer is arranged between the resistor and the dummy gate electrode and an upper plate over the lower plate where a second insulating layer is arranged between the lower and upper plates, are simultaneously formed. A metal silicide layer is then formed over the dummy gate electrode, the resistor, the gate electrode, the junction regions and the lower and upper plates of the analog capacitor.
摘要翻译：公开了一种半导体器件及其制造方法。在形成隔离膜的基板上同时形成电阻器，模拟电容器的下板和MOS晶体管的栅电极。接合区形成在基板的栅极的两侧。同时形成电阻器上方的虚设栅电极，其中第一绝缘层布置在电阻器和伪栅电极之间，并且在下板上设置第二绝缘层，位于下板和上板之间。然后在模拟电容器的伪栅电极，电阻器，栅极电极，接合区域和下部和上部板上形成金属硅化物层。

3. 发明授权

US06413816B2 Method for forming memory cell of semiconductor memory device 失效
标题翻译：用于形成半导体存储器件的存储单元的方法
公开(公告)号：US06413816B2
公开(公告)日：2002-07-02
申请号：US09747793
申请日：2000-12-22
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L21/76802 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L28/60
摘要： A method for fabricating a semiconductor memory device. The method includes providing a semiconductor substrate where a transistor has been formed; forming a bit line electrically connected to a second contact plug on a drain region and forming a contact hole exposing a first contact plug on a source region; forming an etch barrier film having a uniform thickness at the inner walls of the contact hole and on the bit line; forming an interlayer insulation film; forming a storage electrode contact by etching the interlayer insulation film and the etch barrier film on the first contact plug; forming a third contact plug electrically connected to the first contact plug in the storage electrode contact; and forming on the third contact plug a capacitor having a stacked structure of a storage electrode, and a dielectric film and a plate electrode surrounding the storage electrode.
摘要翻译：一种制造半导体存储器件的方法。该方法包括提供其中已形成晶体管的半导体衬底; 形成电连接到漏极区上的第二接触插塞的位线，并形成在源极区域上露出第一接触插塞的接触孔; 在接触孔的内壁和位线上形成均匀厚度的蚀刻阻挡膜; 形成层间绝缘膜; 通过蚀刻第一接触插塞上的层间绝缘膜和蚀刻阻挡膜形成存储电极接触; 形成与所述存储电极接触件中的所述第一接触插头电连接的第三接触插塞; 以及在所述第三接触插塞上形成具有存储电极堆叠结构的电容器，以及围绕所述存储电极的电介质膜和平板电极。

4. 发明授权

US06372565B2 Method of manufacturing SRAM cell 有权
标题翻译：制造SRAM单元的方法
公开(公告)号：US06372565B2
公开(公告)日：2002-04-16
申请号：US09756060
申请日：2001-01-08
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L218238
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.
摘要翻译：本发明公开了具有减小的单元尺寸的静态随机存取存储单元及其制造方法。根据本发明，SRAM单元包括：字线和位线; 连接到字线和位线的存取装置，其中在选择字线的情况下，存取装置输出从位线输入的数据; 连接到接入设备的上拉设备以及预定的电源电压，其中上拉设备根据从接入设备输入的数据以上拉的方式工作; 以及连接到接入设备和上拉设备以及接地的下拉设备，其中下拉设备根据从接入设备输入的数据以下拉方式工作。

5. 发明授权

US6163054A SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US6163054A
公开(公告)日：2000-12-19
申请号：US318369
申请日：1999-05-25
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L27/01
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： The present invention introduces an SRAM cell which enhances immunity to soft errors and a manufacturing method thereof. A method of manufacturing an SRAM cell having access devices, pull-up devices and pull-down devices and forming a cell node junction in common junction regions of the pull-down devices and the access devices, the manufacturing method including the steps of: providing a semiconductor substrate of which active regions are difined and gate insulating layers and gates are formed on thereof; forming N.sup.- junction regions in the substrates of both sides of the gates for the pull-down devices region and the access devices region, wherein the N.sup.- junction regions formed in the cell node are separated therein and are adjacent to the gates thereof; forming the insulating layer spacers on both side-walls of the gates; and forming N.sup.+ junction regions in the substrate of both side of the spacers for the pull-down devices region and the access devices region.
摘要翻译：本发明引入了提高对软错误的抗扰性的SRAM单元及其制造方法。一种制造具有接入装置，上拉装置和下拉装置并在下拉装置和接入装置的公共连接区域中形成小区节点结的SRAM单元的方法，其制造方法包括以下步骤：提供在其上形成活性区域的半导体衬底和形成栅极绝缘层和栅极的半导体衬底; 在用于下拉器件区域和访问器件区域的栅极的两侧的衬底中形成N结区域，其中形成在单元节点中的N结区域在其中分离并且与其栅极相邻; 在门的两个侧壁上形成绝缘层间隔物; 以及在用于下拉装置区域和进入装置区域的隔板的两侧的基板中形成N +结区域。

6. 发明授权

US5953603A Method for manufacturing BiCMOS 失效
标题翻译：制造BiCMOS的方法
公开(公告)号：US5953603A
公开(公告)日：1999-09-14
申请号：US103828
申请日：1998-06-24
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L21/328 , H01L21/8249 , H01L27/06 , H01L29/76
CPC分类号： H01L21/8249
摘要： Disclosed is a method for manufacturing a BiCMOS in which a complementary MOS transistor and a bipolar transistor are formed on the same substrate, comprising the steps of: providing a semiconductor substrate with impurities of a first conductivity type; forming field oxides for device isolation at the substrate to define a first group active region having two active regions and a second group active region having five active regions in series arrangement; forming a first mask pattern to expose three central active regions of the second group active region; forming a buried layer of a second conductivity type at a first depth from surfaces of the three central active regions using the first mask pattern; forming a second mask pattern to expose either one active region of the first group active region and two active regions at both edge portions of the second group active region; forming first well regions of the second conductivity type in which the impurities of the second conductivity type are distributed to a second depth from surfaces of the two exposed active regions of the second group active region using the second mask pattern, wherein the first well regions are overlapped with the buried layer; forming a third mask pattern to expose a remaining active region of the first group active region; and forming a second well in which the impurities of the first conductivity type are distributed at a third depth from a surface of the remaining active region using the third mask pattern.
摘要翻译：公开了一种制造BiCMOS的方法，其中在同一基板上形成互补MOS晶体管和双极晶体管，包括以下步骤：为半导体衬底提供具有第一导电类型的杂质; 形成用于在衬底上器件隔离的场氧化物以限定具有两个有源区的第一组有源区和具有串联布置的五个有源区的第二组有源区; 形成第一掩模图案以暴露所述第二组有源区域的三个中心有源区; 使用所述第一掩模图案在所述三个中心有源区域的表面的第一深度处形成第二导电类型的掩埋层; 形成第二掩模图案以暴露所述第一组有源区的一个有源区和所述第二组有源区的两个边缘部分处的两个有源区; 形成第二导电类型的第一阱区，其中第二导电类型的杂质使用第二掩模图案从第二组有源区的两个曝光的有源区的表面分布到第二深度，其中第一阱区是与埋层重叠; 形成第三掩模图案以暴露所述第一组有源区的剩余有源区; 并且使用第三掩模图案形成其中第一导电类型的杂质从剩余有源区域的表面在第三深度分布的第二阱。

7. 发明授权

US5939757A Semiconductor device having triple well structure 失效
标题翻译：具有三重阱结构的半导体器件
公开(公告)号：US5939757A
公开(公告)日：1999-08-17
申请号：US876351
申请日：1997-06-26
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/76 , H01L29/94
CPC分类号： H01L27/088 , H01L27/0922
摘要： The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.
摘要翻译：本发明公开了一种具有三重阱结构的半导体器件。半导体器件包括：N型杂质掺杂掩埋层，形成在距离第一有源区的表面预定深度的半导体衬底中; 形成在与所述第一有源区相邻的所述第二有源区下方的第一P型阱区; 形成在所述半导体衬底中从所述第一有源区的表面的深度的第二P型阱区; 形成在第三有源区下面的第一N型阱区; 形成在所述隔离膜的选定部分下方限定第一有源区和所述第二有源区的第二N型阱区; 以及分别在第一有源区的表面正下方形成的第二P型掺杂区和第二N型掺杂区，并且紧邻第二有源区的表面，其中第一掺杂区的掺杂浓度低于第二掺杂区域。

8. 发明授权

US5478770A Methods for manufacturing a storage electrode of DRAM cells 失效
标题翻译：制造DRAM单元的存储电极的方法
公开(公告)号：US5478770A
公开(公告)日：1995-12-26
申请号：US415330
申请日：1995-04-03
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L21/28 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A method for manufacturing a storage electrode of DRAM cells having a higher degree of integration in which the space between neighboring storage electrodes is made narrower than that obtainable by conventional lithographic techniques. The storage electrode is formed with a cylindrical, dual cylindrical, or jar-shaped structure to obtain a large surface area, and thus a high-capacitance.
摘要翻译：制造具有较高集成程度的DRAM单元的存储电极的方法，其中相邻存储电极之间的空间比通过常规光刻技术获得的更窄。存储电极形成为具有圆柱形，双圆柱形或瓶形结构，以获得大的表面积，因此具有高电容。

9. 发明授权

US06689656B2 Dynamic random access memory and the method for fabricating thereof 失效
标题翻译：动态随机存取存储器及其制造方法
公开(公告)号：US06689656B2
公开(公告)日：2004-02-10
申请号：US10391046
申请日：2003-03-18
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/1203
摘要： The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interposed an insulation layer between therewith, thereby forming a trench capacitor at a region, which is used to be formed a transistor in the conventional art. Accordingly, when forming the trench capacitors, in which the numbers are the same as the conventional art, at the same silicon substrate area, a trench capacitor with large in diameter and shallow in depth can be formed, thereby performing a trench capacitor forming process. According to the present invention, after forming a trench, successive processes become easy and reliability of device can be enhanced.
摘要翻译：本发明公开了一种动态随机存取存储器及其制造方法。具有沟槽电容器的第一硅衬底和具有晶体管的第二硅衬底形成有双层，其在其间插入有绝缘层，从而在用于形成晶体管的区域形成沟槽电容器常规技术因此，在同一硅衬底区域形成数量与现有技术相同的沟槽电容器时，可以形成直径大且深度浅的沟槽电容器，从而进行沟槽电容器形成工序。根据本发明，在形成沟槽之后，连续的工艺变得容易，并且可以提高器件的可靠性。

10. 发明授权

US06448134B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06448134B2
公开(公告)日：2002-09-10
申请号：US09732109
申请日：2000-12-07
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10852
摘要： Disclosed is a method for fabricating a semiconductor device including stacked capacitors, in which dummy plate electrodes and charge storage electrodes are formed at a region other than a memory cell region, to control a topology resulting from capacitors, thereby allowing fine interconnection lines to be formed after the formation of those capacitors. In accordance with this method, dummy plate electrodes and charge storage electrodes, each of which has the same height as that of the stacked capacitor, are formed at the logic circuit region when the stacked capacitor are formed at the memory cell region.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件包括层叠电容器，其中在存储单元区域以外的区域形成有虚设板电极和电荷存储电极，以控制由电容器产生的拓扑，从而允许形成精细的互连线之后形成这些电容。根据该方法，当堆叠电容器形成在存储单元区域时，在逻辑电路区域形成有与叠层电容器的高度相同的虚拟板电极和电荷存储电极。

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