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1. 发明授权

US09191015B2 Temperature controlled oscillator and temperature sensor including the same 有权
标题翻译：温度控制振荡器和温度传感器包括相同的
公开(公告)号：US09191015B2
公开(公告)日：2015-11-17
申请号：US14159492
申请日：2014-01-21
申请人： Sung-Jin Kim , Jae-Jin Park
发明人： Sung-Jin Kim , Jae-Jin Park
IPC分类号： H03K3/0231 , H03L7/00 , H03L1/02 , H03B5/24
CPC分类号： H03L7/00 , H03B5/24 , H03L1/022
摘要： A temperature controlled oscillator includes an oscillation unit and a filter unit. The oscillation unit is configured to generate at least one reference voltage based on a supply voltage and a ground voltage, and to generate an oscillation signal having a period varying according to a temperature, the oscillation unit configured to generate the oscillation signal based on a filter voltage and the at least one reference voltage. The filter unit is configured to generate the filter voltage based on the oscillation signal.
摘要翻译：温度控制振荡器包括振荡单元和滤波器单元。振荡单元被配置为基于电源电压和接地电压产生至少一个参考电压，并且产生具有根据温度变化的周期的振荡信号，所述振荡单元被配置为基于滤波器产生振荡信号电压和至少一个参考电压。滤波器单元被配置为基于振荡信号产生滤波电压。

2. 发明授权

US08935551B2 Supply voltage generator for a display timing controller with current reuse 有权
标题翻译：用于具有当前重用的显示定时控制器的电源电压发生器
公开(公告)号：US08935551B2
公开(公告)日：2015-01-13
申请号：US13475043
申请日：2012-05-18
申请人： Wang Yu , Jae-Youl Lee , Jae-Jin Park
发明人： Wang Yu , Jae-Youl Lee , Jae-Jin Park
IPC分类号： G06F1/32 , G09G5/00 , H03K19/00 , G09G3/36 , G06F1/26 , G09G3/38
CPC分类号： H03K19/0013 , G06F1/26 , G09G3/3611 , G09G3/38
摘要： A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.
摘要翻译：一种包括电源电压发生器，一个或多个第一电路块和一个或多个第二电路块的半导体IC。电源电压发生器被配置为基于外部电源电压产生第一电源电压和第二电源电压，并且将第一电源电压提供给第一电源总线，并将第二电源电压提供给第二电力总线。第一电路块连接在第一电源总线和第二电源总线之间，第二电路块连接在第二电源总线和地之间。

3. 发明申请

US20120319765A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SUPPLYING POWER TO THE SAME 有权
标题翻译：半导体集成电路及其供电方法
公开(公告)号：US20120319765A1
公开(公告)日：2012-12-20
申请号：US13475043
申请日：2012-05-18
申请人： Wang Yu , Jae-Youl Lee , Jae-Jin Park
发明人： Wang Yu , Jae-Youl Lee , Jae-Jin Park
IPC分类号： G05F3/02
CPC分类号： H03K19/0013 , G06F1/26 , G09G3/3611 , G09G3/38
摘要： A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.
摘要翻译：一种包括电源电压发生器，一个或多个第一电路块和一个或多个第二电路块的半导体IC。电源电压发生器被配置为基于外部电源电压产生第一电源电压和第二电源电压，并且将第一电源电压提供给第一电源总线，并将第二电源电压提供给第二电力总线。第一电路块连接在第一电源总线和第二电源总线之间，第二电路块连接在第二电源总线和地之间。

4. 发明授权

US08314763B2 Display device transferring data signal with clock 有权
标题翻译：显示设备用时钟传输数据信号
公开(公告)号：US08314763B2
公开(公告)日：2012-11-20
申请号：US12167393
申请日：2008-07-03
申请人： Jae-Jin Park , Dong-Uk Park , Jin-Ho Seo
发明人： Jae-Jin Park , Dong-Uk Park , Jin-Ho Seo
IPC分类号： G09G3/36
CPC分类号： G09G3/2096 , G09G3/3685 , G09G5/008 , G09G2330/06
摘要： A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.
摘要翻译：显示装置包括：面板，产生组合图像数据和时钟信号的嵌入式时钟数据信号的定时控制器和响应于嵌入的时钟数据信号驱动面板的列驱动器。嵌入式时钟数据信号中的数据位以三电平信令方案中的三个电压电平中的一个通信，并且定时控制器确定嵌入式时钟数据信号中当前数据位（DIN [n]）的三个电压电平之一时钟数据信号相对于嵌入式时钟数据信号中的先前数据位（DIN [n-1]）的电压电平。

5. 发明申请

US20120183104A1 DIGITAL PHASE FREQUENCY DETECTOR, DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME AND METHOD OF DETECTING PHASE AND FREQUENCY OF OUTPUT SIGNAL 有权
标题翻译：数字相位频率检测器，数字相位锁定环路及其相位检测和输出信号频率检测方法
公开(公告)号：US20120183104A1
公开(公告)日：2012-07-19
申请号：US13315476
申请日：2011-12-09
申请人： JONG-PHIL HONG , Ji-Hyun Kim , Jae-Jin Park
发明人： JONG-PHIL HONG , Ji-Hyun Kim , Jae-Jin Park
IPC分类号： H04L27/06
CPC分类号： H03L7/113 , H03L7/085 , H03L7/1077
摘要： A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.
摘要翻译：数字相位频率检测器包括检测单元，复位单元和相位比较单元。检测单元检测参考信号和反馈输入信号的边沿以产生参考边缘信号和反馈边缘信号。复位单元基于参考边沿信号和反馈边沿信号产生复位检测单元的复位信号。相位比较单元基于参考边缘信号和反馈边缘信号产生第一和第二相位比较信号。相位比较单元包括基于参考边缘信号和反馈边缘信号产生第一比较信号的第一触发器，基于参考边缘信号和反馈边缘信号产生第二比较信号的第二触发器，以及锁存块锁存第一和第二比较信号以产生第一和第二相位比较信号。

6. 发明授权

US09467135B2 System-on-chip including body bias voltage generator 有权
标题翻译：系统级芯片包括体偏置电压发生器
公开(公告)号：US09467135B2
公开(公告)日：2016-10-11
申请号：US14717379
申请日：2015-05-20
申请人： Sang-Kyu Kim , Jae-Jin Park , Seung-Hoon Lee
发明人： Sang-Kyu Kim , Jae-Jin Park , Seung-Hoon Lee
IPC分类号： H03K17/00 , H03K17/041 , H03K17/14 , H03K17/16
CPC分类号： H03K17/04106 , H03K17/145 , H03K17/162 , H03K2217/0018
摘要： A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage.
摘要翻译：芯片上系统包括具有分压器和滤波器的体偏置电压发生器。分压器包括开关电容电路和电阻电路。开关电容器电路基于第一时钟信号和第二时钟信号进行工作。电阻电路通过第一节点输出第一电压，该第一节点耦合到开关电容器电路和电阻电路。第一和第二时钟信号具有相同的频率。滤波器对第一电压进行滤波操作以产生体偏置电压。

7. 发明申请

US20160049928A1 SYSTEM-ON-CHIP INCLUDING BODY BIAS VOLTAGE GENERATOR 有权
标题翻译：系统芯片，包括身体偏压发电机
公开(公告)号：US20160049928A1
公开(公告)日：2016-02-18
申请号：US14717379
申请日：2015-05-20
申请人： Sang-Kyu KIM , Jae-Jin PARK , Seung-Hoon LEE
发明人： Sang-Kyu KIM , Jae-Jin PARK , Seung-Hoon LEE
IPC分类号： H03K17/041
CPC分类号： H03K17/04106 , H03K17/145 , H03K17/162 , H03K2217/0018
摘要： A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage.
摘要翻译：片上系统包括具有分压器和滤波器的体偏置电压发生器。分压器包括开关电容电路和电阻电路。开关电容器电路基于第一时钟信号和第二时钟信号进行工作。电阻电路通过第一节点输出第一电压，该第一节点耦合到开关电容器电路和电阻电路。第一和第二时钟信号具有相同的频率。滤波器对第一电压进行滤波操作以产生体偏置电压。

8. 发明授权

US09041443B2 Digital phase-locked loop using phase-to-digital converter, method of operating the same, and devices including the same 有权
标题翻译：使用数模转换器的数字锁相环，其操作方法以及包括其的装置
公开(公告)号：US09041443B2
公开(公告)日：2015-05-26
申请号：US14182812
申请日：2014-02-18
申请人： Tae Kwang Jang , Jenlung Liu , Nan Xing , Jae Jin Park
发明人： Tae Kwang Jang , Jenlung Liu , Nan Xing , Jae Jin Park
IPC分类号： H03L7/06 , H03L7/085
CPC分类号： H03L7/085 , H03L7/0995 , H03L7/113 , H03L7/18 , H03L7/193 , H03L7/1976 , H03L2207/50
摘要： A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.
摘要翻译：提供数字锁相环（DPLL），其操作方法以及包括该锁相环的装置。 DPLL包括数字控制振荡器，其被配置为响应于数字控制码改变输出振荡信号的频率和相位; 主分压器，被配置为分频输出振荡信号的频率，并基于分频产生第一反馈信号; 以及相位数字转换器，其被配置为细分输出振荡信号的相位，并且通过使用由细分产生的相位细分信号转换参考信号和第一反馈信号之间的相位差来产生量化代码。数字控制码是基于量化码产生的。

9. 发明申请

US20140266355A1 PHASE-LOCKED LOOP, METHOD OF OPERATING THE SAME, AND DEVICES HAVING THE SAME 有权
标题翻译：相位锁定环，其操作方法和具有该环的装置
公开(公告)号：US20140266355A1
公开(公告)日：2014-09-18
申请号：US14201285
申请日：2014-03-07
申请人： Jae Jin PARK , Tae Kwang JANG , Jenlung LIU
发明人： Jae Jin PARK , Tae Kwang JANG , Jenlung LIU
IPC分类号： H03L7/10
CPC分类号： H03L7/10 , H03L7/095 , H03L7/0997 , H03L2207/50
摘要： A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.
摘要翻译：操作诸如全数字PLL的锁相环（PLL）的方法包括将参考时钟信号与PLL的反馈信号进行比较并根据比较结果输出比较信号的操作，以及检测是否 PLL通过使用比较信号切换的次数处于锁定状态。

10. 发明申请

US20140266346A1 ALL-DIGITAL PHASE-LOCKED LOOP FOR ADAPTIVELY CONTROLLING CLOSED-LOOP BANDWIDTH, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME 有权
标题翻译：用于适应性控制闭环带宽的全数字锁相环，其操作方法和包括其的设备
公开(公告)号：US20140266346A1
公开(公告)日：2014-09-18
申请号：US14204251
申请日：2014-03-11
申请人： Jae Jin PARK , Tae Kwang JANG , Nan XING , Jen Lung LIU
发明人： Jae Jin PARK , Tae Kwang JANG , Nan XING , Jen Lung LIU
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/095 , H03L7/0997 , H03L7/10 , H03L2207/50
摘要： A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window.
摘要翻译：一种操作全数字锁相环（ADPLL）的方法包括使用搜索窗口检测ADPLL的反馈信号中的相位变化，并且基于检测结果来控制ADPLL的闭环带宽。当在搜索窗口内检测到相位变化时，在搜索窗口之外检测到相位变化时的闭环带宽大于闭环带宽。

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