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1. 发明申请

US20120306551A1 CIRCUIT AND METHOD FOR PREVENTING FALSE LOCK AND DELAY LOCKED LOOP USING THE SAME 有权
标题翻译：用于防止锁定和延迟锁定环路的电路和方法
公开(公告)号：US20120306551A1
公开(公告)日：2012-12-06
申请号：US13482948
申请日：2012-05-29
申请人： Yong Hwan MOON , Young Soo RYU , Jae Ryun SHIM , Chul Soo JEONG , Sang Ho KIM
发明人： Yong Hwan MOON , Young Soo RYU , Jae Ryun SHIM , Chul Soo JEONG , Sang Ho KIM
IPC分类号： H03L7/08 , H03L7/00
CPC分类号： H03L7/0814
摘要： The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.
摘要翻译：本发明涉及一种假锁防止电路和方法，用于在DLL中发生错误锁定时使延迟锁定环（DLL）逃避诸如谐波锁定或卡锁的假锁，以及使用一样。该假锁防止电路包括配置成检测谐波锁定的谐波锁定检测器和被配置为检测卡锁的卡锁锁定检测器。谐波锁定检测器包括被配置为对多个延迟时钟进行采样的多个触发器和逻辑单元。谐波锁定检测器将参考时钟信号与多个延迟的时钟信号进行比较，并且检测正边缘是否偏离参考时钟信号的一个周期。

2. 发明授权

US5996081A System having series controllers for controlling suspending of power to associate core blocks based on suspending signal and signal indicators that the converted data is invalid 失效
标题翻译：具有串行控制器的系统，其基于挂起信号和信号指示符来控制暂停核心块的功率以使转换的数据无效
公开(公告)号：US5996081A
公开(公告)日：1999-11-30
申请号：US31680
申请日：1998-02-27
申请人： Jae Ryun Shim
发明人： Jae Ryun Shim
IPC分类号： G06F1/30 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： An apparatus for suspending power of a processing system having a plurality of core blocks connected in series includes a system controller which receives input data and determines whether to suspend a supply of power to the processing system based on the input data. A converter converts a format of the input data, and a determining unit determines whether the converted input data is valid data. Valid data is data which will be processed by the plurality of core blocks. A series of controllers in the apparatus shift output from the determining unit through the series of controllers. Each controller temporarily stores the output from the determining unit prior to shifting the output from the determining unit to a next controller in the series of controllers. Also, each controller is associated with one of the plurality of core blocks, and controls a supply of power to the associated core block based on output from the system controller and the output from the determining unit temporarily stored therein.
摘要翻译：用于暂停具有串联连接的多个核心块的处理系统的电力的装置包括系统控制器，其接收输入数据并基于输入数据确定是否暂停向处理系统供电。 A转换器转换输入数据的格式，并且确定单元确定转换的输入数据是否是有效数据。有效数据是将被多个核心块处理的数据。设备中的一系列控制器通过一系列控制器从确定单元输出输出。每个控制器在将所述确定单元的输出移动到所述一系列控制器中的下一个控制器之前，临时存储来自所述确定单元的输出。此外，每个控制器与多个核心块中的一个相关联，并且基于系统控制器的输出和暂时存储在其中的确定单元的输出来控制对相关联的核心块的供电。

3. 发明授权

US08698527B2 Circuit and method for preventing false lock and delay locked loop using the same 有权
标题翻译：用于防止假锁定和延迟锁定环路的电路和方法
公开(公告)号：US08698527B2
公开(公告)日：2014-04-15
申请号：US13482948
申请日：2012-05-29
申请人： Yong Hwan Moon , Young Soo Ryu , Jae Ryun Shim , Chul Soo Jeong , Sang Ho Kim
发明人： Yong Hwan Moon , Young Soo Ryu , Jae Ryun Shim , Chul Soo Jeong , Sang Ho Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.
摘要翻译：本发明涉及一种假锁防止电路和方法，用于在DLL中发生错误锁定时使延迟锁定环（DLL）逃避诸如谐波锁定或卡锁的假锁，以及使用一样。该假锁防止电路包括配置成检测谐波锁定的谐波锁定检测器和被配置为检测卡锁的卡锁锁定检测器。谐波锁定检测器包括被配置为对多个延迟时钟进行采样的多个触发器和逻辑单元。谐波锁定检测器将参考时钟信号与多个延迟的时钟信号进行比较，并且检测正边缘是否偏离参考时钟信号的一个周期。

4. 发明申请

US20120194224A1 PRE-EMPHASIS CIRCUIT AND DIFFERENTIAL CURRENT SIGNALING SYSTEM HAVING THE SAME 有权
标题翻译：具有相同功能的前置放大电路和差分电流信号系统
公开(公告)号：US20120194224A1
公开(公告)日：2012-08-02
申请号：US13357224
申请日：2012-01-24
申请人： Yong-Hwan Moon , Jun-Ho Kim , Jae-Ryun Shim , Chul-Soo Jeong , Sang-Ho Kim
发明人： Yong-Hwan Moon , Jun-Ho Kim , Jae-Ryun Shim , Chul-Soo Jeong , Sang-Ho Kim
IPC分类号： H03K17/00
CPC分类号： H03K17/162 , H03K5/1515 , H04L25/03343
摘要： Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.
摘要翻译：提供了一种预加重电路，其响应于通过差分输入信号的逻辑运算产生的第一至第四预加重控制信号，将预加重输出电流发送到输出驱动器的输出节点。预加重电路包括：第一预加重电路，其在第一电压和第二电压之间的范围内被驱动，并且被配置为响应于第一和第二预加重控制信号产生第一预加重输出电流并输出生成的第一预加重输出电流到输出驱动器的第一输出节点; 以及第二预加重电路，其在所述第一电压和所述第二电压之间的范围内被驱动，并被配置为响应于所述第三和第四预加重控制信号产生第二预加重输出电流，并输出所生成的第二预加重将输出电流输出到输出驱动器的第二输出节点。

5. 发明授权

US08659329B2 Pre-emphasis circuit and differential current signaling system having the same 有权
标题翻译：预加重电路和差分电流信号系统具有相同的功能
公开(公告)号：US08659329B2
公开(公告)日：2014-02-25
申请号：US13357224
申请日：2012-01-24
申请人： Yong Hwan Moon , Jun Ho Kim , Jae Ryun Shim , Chul Soo Jeong , Sang Ho Kim
发明人： Yong Hwan Moon , Jun Ho Kim , Jae Ryun Shim , Chul Soo Jeong , Sang Ho Kim
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K17/162 , H03K5/1515 , H04L25/03343
摘要： Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.
摘要翻译：提供了一种预加重电路，其响应于通过差分输入信号的逻辑运算产生的第一至第四预加重控制信号，将预加重输出电流发送到输出驱动器的输出节点。预加重电路包括：第一预加重电路，其在第一电压和第二电压之间的范围内被驱动，并且被配置为响应于第一和第二预加重控制信号产生第一预加重输出电流并输出生成的第一预加重输出电流到输出驱动器的第一输出节点; 以及第二预加重电路，其在所述第一电压和所述第二电压之间的范围内被驱动，并被配置为响应于所述第三和第四预加重控制信号产生第二预加重输出电流，并输出所生成的第二预加重将输出电流输出到输出驱动器的第二输出节点。

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