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1. 发明授权

US08446757B2 Spin-torque transfer magneto-resistive memory architecture 有权
标题翻译：自旋扭矩传递磁阻存储器架构
公开(公告)号：US08446757B2
公开(公告)日：2013-05-21
申请号：US12858879
申请日：2010-08-18
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种存储器阵列器件，包括第一存储器单元，该第一存储器单元包括具有连接到第一位线（BLTE）的第一端子和第二端子的第一磁性隧道结器件，以及具有与源极端子连接的第一场效应晶体管第二位线（BLC），连接到字线（WL）的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及第二存储单元，其包括：第二磁性隧道结装置，连接到第三位线（BLT0）和第二端子的第一端子和具有连接到第二位线（BLC）的源极端子的第二场效应晶体管（FET），连接到字线（WL）的栅极端子）和连接到第二磁性隧道结装置的第二端子的漏极端子。

2. 发明申请

US20120294071A1 Spin-Torque Transfer Magneto-Resistive Memory Architecture 失效
标题翻译：自旋转移磁阻存储器架构
公开(公告)号：US20120294071A1
公开(公告)日：2012-11-22
申请号：US13559672
申请日：2012-07-27
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种系统包括处理器和连接到处理器的存储器阵列，该存储器阵列包括第一存储器单元，该第一存储器单元包括具有连接到第一位线的第一端子和第二端子的第一磁性隧道结器件，以及具有源极端子的第一场效应晶体管连接到第二位线，连接到字线的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及包括第二磁性隧道结装置的第二存储单元，第二磁性隧道结装置具有第一端子连接至第三位线和第二端子，以及第二场效应晶体管，其源极端子连接到第二位线，连接到字线的栅极端子和连接到第二磁通道的第二端子的漏极端子连接装置。

3. 发明申请

US20120044754A1 Spin-Torque Transfer Magneto-Resistive Memory Architecture 有权
标题翻译：自旋转移磁阻存储器架构
公开(公告)号：US20120044754A1
公开(公告)日：2012-02-23
申请号：US12858879
申请日：2010-08-18
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种存储器阵列器件，包括第一存储器单元，该第一存储器单元包括具有连接到第一位线（BLTE）的第一端子和第二端子的第一磁性隧道结器件，以及具有与源极端子连接的第一场效应晶体管第二位线（BLC），连接到字线（WL）的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及第二存储单元，其包括：第二磁性隧道结装置，连接到第三位线（BLT0）和第二端子的第一端子和具有连接到第二位线（BLC）的源极端子的第二场效应晶体管（FET），连接到字线（WL）的栅极端子）和连接到第二磁性隧道结装置的第二端子的漏极端子。

4. 发明授权

US07514271B2 Method of forming high density planar magnetic domain wall memory 有权
标题翻译：形成高密度平面磁畴壁记忆的方法
公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00 , G11C5/12 , G11C11/14
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译：形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。

5. 发明申请

US20090086534A1 APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES 失效
标题翻译：用于实施PCRAM设备精密感测的装置和方法
公开(公告)号：US20090086534A1
公开(公告)日：2009-04-02
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
IPC分类号： G11C11/00 , G11C7/00 , G11C7/10
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

6. 发明授权

US06351019B1 Planarized and fill biased integrated circuit chip 有权
标题翻译：平面化和补偿偏置集成电路芯片
公开(公告)号：US06351019B1
公开(公告)日：2002-02-26
申请号：US09585503
申请日：2000-06-01
申请人： John K. DeBrosse , Matthew R. Wordeman
发明人： John K. DeBrosse , Matthew R. Wordeman
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/82 , H01L27/0629
摘要： An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.
摘要翻译：一种用于集成电路芯片和芯片设计的隔离栅极平面化方法。该方法包括产生虚拟栅极导体（GC）形状并将其偏压到下面的阱。该方法还可以包括生成下面的GC虚拟形状的有源区（AA）虚拟形状。偏置可能与下面的阱具有相同的电压，或者可以是不同的电压以产生去耦电容器。偏置可以通过在有源区域形状上注入阱接触来实现，该触点是通过P阱的N阱或P +上的N +。

7. 发明授权

US5525531A SOI DRAM with field-shield isolation 失效
标题翻译：具有场屏蔽隔离的SOI DRAM
公开(公告)号：US5525531A
公开(公告)日：1996-06-11
申请号：US461815
申请日：1995-06-05
申请人： Gary B. Bronner , John K. DeBrosse , Jack A. Mandelman
发明人： Gary B. Bronner , John K. DeBrosse , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L27/10829 , H01L27/1203
摘要： An SOI deep-trench DRAM having body contacts and field shield isolation makes contact between the SOI device layer and a buried conductive layer below the insulating layer at selected sites between adjacent deep trench capacitors. The buried layer may be biased to provide better attraction for holes.
摘要翻译：具有体接触和场屏蔽隔离的SOI深沟槽DRAM在相邻的深沟槽电容器之间的选定位置处与SOI器件层和绝缘层下方的掩埋导电层之间接触。掩埋层可能被偏置以为孔提供更好的吸引力。

8. 发明授权

US5508219A SOI DRAM with field-shield isolation and body contact 失效
标题翻译： SOI DRAM具有屏蔽隔离和机身接触
公开(公告)号：US5508219A
公开(公告)日：1996-04-16
申请号：US461958
申请日：1995-06-05
申请人： Gary B. Bronner , John K. DeBrosse , Jack A. Mandelman
发明人： Gary B. Bronner , John K. DeBrosse , Jack A. Mandelman
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/12
CPC分类号： H01L27/10861 , H01L27/1203
摘要： An SOI deep-trench DRAM having body contacts and field shield isolation makes contact between the SOI device layer and the field shield layer at selected sites between adjacent deep trench capacitors. The field shield layer is biased negative to provide better isolation and to set the body potential of the array transistors.
摘要翻译：具有体接触和场屏蔽隔离的SOI深沟槽DRAM在相邻的深沟槽电容器之间的选定位置处与SOI器件层和场屏蔽层之间接触。场屏蔽层被偏置为负极以提供更好的隔离并且设置阵列晶体管的体电位。

9. 发明授权

US08456901B2 Spin-torque transfer magneto-resistive memory architecture 失效
标题翻译：自旋扭矩传递磁阻存储器架构
公开(公告)号：US08456901B2
公开(公告)日：2013-06-04
申请号：US13559672
申请日：2012-07-27
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种系统包括处理器和连接到处理器的存储器阵列，该存储器阵列包括第一存储器单元，该第一存储器单元包括具有连接到第一位线的第一端子和第二端子的第一磁性隧道结器件，以及具有源极端子的第一场效应晶体管连接到第二位线，连接到字线的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及包括第二磁性隧道结装置的第二存储单元，第二磁性隧道结装置具有第一端子连接至第三位线和第二端子，以及第二场效应晶体管，其源极端子连接到第二位线，连接到字线的栅极端子和连接到第二磁通道的第二端子的漏极端子连接装置。

10. 发明授权

US08023305B2 High density planar magnetic domain wall memory apparatus 有权
标题翻译：高密度平面磁畴壁存储装置
公开(公告)号：US08023305B2
公开(公告)日：2011-09-20
申请号：US12136091
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/02 , G11C19/08
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

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