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1. 发明申请

US20100050145A1 Optimizing a Netlist Circuit Representation by Leveraging Binary Decision Diagrams to Perform Rewriting 有权
标题翻译：通过利用二进制决策图进行重写来优化网表电路表示
公开(公告)号：US20100050145A1
公开(公告)日：2010-02-25
申请号：US12197980
申请日：2008-08-25
申请人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.
摘要翻译：利用现有的二进制决策图（BDD）来增强代表作为网表的状态机的系统模型中的电路减少。评估网表以确定潜力最大的地区。执行BDD扫描以识别网表中的冗余。 BDD重写通过用更有效的等效逻辑替换原始网表的门来实现电路减少。

2. 发明申请

US20080092104A1 Method for Improved Synthesis of Binary Decision Diagrams with Inverted Edges and Quantifiable as Well as Nonquantifiable Variables 有权
公开(公告)号：US20080092104A1
公开(公告)日：2008-04-17
申请号：US11953419
申请日：2007-12-10
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.

3. 发明申请

US20080091386A1 Method and System for Reduction of XOR/XNOR Subexpressions in Structural Design Representations 有权
标题翻译：减少XOR / XNOR子表达式在结构设计表示中的方法和系统
公开(公告)号：US20080091386A1
公开(公告)日：2008-04-17
申请号：US11955152
申请日：2007-12-12
申请人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译：公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减设计包含减少数量的异或门。确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定缩减设计的尺寸小于初始设计的尺寸，初始设计被替换为减少设计。

4. 发明申请

US20080077381A1 System for Verification of Digital Designs Using Case-Splitting via Constrained Internal Signals 失效
标题翻译：用于通过约束内部信号使用案例分解验证数字设计的系统
公开(公告)号：US20080077381A1
公开(公告)日：2008-03-27
申请号：US11944956
申请日：2007-11-26
申请人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。

5. 发明申请

US20080072185A1 Method and System for Reduction of AND/OR Subexpressions in Structural Design Representations 有权
公开(公告)号：US20080072185A1
公开(公告)日：2008-03-20
申请号：US11944663
申请日：2007-11-26
申请人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.

6. 发明申请

US20080052648A1 METHOD AND SYSTEM FOR ENCHANCED VERIFICATION THROUGH BINARY DECISION DIAGRAM-BASED TARGET DECOMPOSITION 有权
标题翻译：通过二进制决策图目标分解进行加强验证的方法和系统
公开(公告)号：US20080052648A1
公开(公告)日：2008-02-28
申请号：US11848356
申请日：2007-08-31
申请人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
摘要翻译：公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。该方法包括接收包括第一目标组，主要输入集和包括一个或多个寄存器的第一寄存器组的设计。生成设计的二进制决策图分析。使用第一目标集合和主要输入集合的二进制判定图分析来生成所选寄存器的一个或多个下一个状态的递归提取。递归提取被分解以产生第二目标集合，并且验证第二目标集合。

7. 发明申请

US20070174798A1 Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver 有权
标题翻译：通过紧密耦合结构过近似算法和结构可满足性求解器来增强验证的方法和系统
公开(公告)号：US20070174798A1
公开(公告)日：2007-07-26
申请号：US11340477
申请日：2006-01-26
申请人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.
摘要翻译：公开了一种用于执行验证的方法，系统和计算机程序产品。创建包含第一个目标的初始设计网表的第一个抽象，并将其指定为当前抽象，并且当前抽象由可选深度展开。使用可满足性求解器验证复合目标，并且响应于确定验证步骤已经击中复合目标，检查反例以识别要被断言的第一目标的一个或多个原因。通过检查反例来构建一个或多个细化对，并通过组合细化对构建第二个抽象。选择一个或多个学习子句和一个或多个第二抽象和第二抽象的不变量作为当前抽象。目前的抽象是用可满足性求解器来验证的。

8. 发明申请

US20060248481A1 Method and system for reversing the effects of sequential reparameterization on traces 有权
标题翻译：用于逆转顺序重新参数化对痕迹的影响的方法和系统
公开(公告)号：US20060248481A1
公开(公告)日：2006-11-02
申请号：US11105616
申请日：2005-04-14
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.
摘要翻译：公开了一种用于逆参数化反转效果的方法，系统和计算机程序产品。该方法包括接收原始设计，抽象设计和抽象设计的第一个跟踪。一个或多个条件值通过抽象设计填充到第一个跟踪中，并且转换k阶可满足性检查以获得第二个跟踪。一个或多个计算值被连接到具有一个或多个已建立值的第二个跟踪中的初始门集合到抽象跟踪中的初始设计的生成子集以形成新的跟踪，并且重新参数化的一个或多个效果被反转通过在初始设计中返回新的轨迹。

9. 发明申请

US20060230366A1 Method and system for reduction of XOR/XNOR subexpressions in structural design representations 失效
标题翻译：在结构设计表示中减少XOR / XNOR子表达式的方法和系统
公开(公告)号：US20060230366A1
公开(公告)日：2006-10-12
申请号：US11086720
申请日：2005-03-22
申请人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Robert Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译：公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减设计包含减少数量的异或门。确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为减少设计。

10. 发明申请

US20060206842A1 Method for retiming in the presence of verification constraints 失效
标题翻译：在存在验证约束的情况下重新定时的方法
公开(公告)号：US20060206842A1
公开(公告)日：2006-09-14
申请号：US11077331
申请日：2005-03-10
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.
摘要翻译：公开了一种用于在存在约束的情况下执行重新定时的方法，系统和计算机程序产品。该方法包括接收包含一个或多个目标和一个或多个约束的初始设计，并将一个或多个约束和一个或多个目标列举到重定时门组中。从初始设计构建重新定时图，并在重新定时图上获得重新定时解决方案。重新定时解决方案被归一化。来自重新定时图的一个或多个重新定时延迟被传播到初始设计，并且通过使用约束满足分析来确认初始设计，以确定在满足一个或多个约束的情况下是否可以命中一个或多个目标。

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