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1. 发明申请

US20100050145A1 Optimizing a Netlist Circuit Representation by Leveraging Binary Decision Diagrams to Perform Rewriting 有权
标题翻译：通过利用二进制决策图进行重写来优化网表电路表示
公开(公告)号：US20100050145A1
公开(公告)日：2010-02-25
申请号：US12197980
申请日：2008-08-25
申请人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.
摘要翻译：利用现有的二进制决策图（BDD）来增强代表作为网表的状态机的系统模型中的电路减少。评估网表以确定潜力最大的地区。执行BDD扫描以识别网表中的冗余。 BDD重写通过用更有效的等效逻辑替换原始网表的门来实现电路减少。

2. 发明授权

US08799837B2 Optimizing a netlist circuit representation by leveraging binary decision diagrams to perform rewriting 有权
标题翻译：通过利用二进制决策图执行重写来优化网表电路表示
公开(公告)号：US08799837B2
公开(公告)日：2014-08-05
申请号：US12197980
申请日：2008-08-25
申请人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.
摘要翻译：利用现有的二进制决策图（BDD）来增强代表作为网表的状态机的系统模型中的电路减少。评估网表以确定潜力最大的地区。执行BDD扫描以识别网表中的冗余。 BDD重写通过用更有效的等效逻辑替换原始网表的门来实现电路减少。

3. 发明授权

US07788618B2 Scalable dependent state element identification 有权
标题翻译：可扩展的依赖状态元素标识
公开(公告)号：US07788618B2
公开(公告)日：2010-08-31
申请号：US11864944
申请日：2007-09-29
申请人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable.
摘要翻译：提供了方法，系统和软件产品，以增强依赖状态分析元素识别的可扩展性。在分配表示状态机的模型的方法中，从模型的变量中选择变量，并且识别支持所选变量的第一组变量。然后，识别出第二组变量具有第一组变量的重叠支持。第二组变量是适用于确定所选变量的可达状态的过近似的分区。

4. 发明申请

US20090089730A1 Scalable Dependent State Element Identification 有权
标题翻译：可扩展的依赖状态元素识别
公开(公告)号：US20090089730A1
公开(公告)日：2009-04-02
申请号：US11864944
申请日：2007-09-29
申请人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Robert Kanzelman , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable.
摘要翻译：提供了方法，系统和软件产品，以增强依赖状态分析元素识别的可扩展性。在分配表示状态机的模型的方法中，从模型的变量中选择变量，并且识别支持所选变量的第一组变量。然后，识别出第二组变量具有第一组变量的重叠支持。第二组变量是适用于确定所选变量的可达状态的过近似的分区。

5. 发明申请

US20080109769A1 Method and System for Reversing the Effects of Sequential Reparameterization on Traces 有权
公开(公告)号：US20080109769A1
公开(公告)日：2008-05-08
申请号：US12013220
申请日：2008-01-11
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

6. 发明申请

US20080104560A1 Method and system for parametric reduction of sequential designs 失效
标题翻译：顺序设计参数化减少的方法和系统
公开(公告)号：US20080104560A1
公开(公告)日：2008-05-01
申请号：US11971283
申请日：2008-01-09
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.
摘要翻译：公开了一种用于执行顺序设计的参数化减少的方法，系统和计算机程序产品。该方法包括接收包括一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。识别包括一个或多个切割门的初始设计的切割，并且计算在一个或多个主要输入和一个或多个状态元素方面可生产到一个或多个切割门的一个或多个值的关系。该关系被合成以形成一个栅极集合，并且从栅极集合形成抽象的设计。对抽象设计进行验证以生成验证结果。

7. 发明申请

US20080092104A1 Method for Improved Synthesis of Binary Decision Diagrams with Inverted Edges and Quantifiable as Well as Nonquantifiable Variables 有权
公开(公告)号：US20080092104A1
公开(公告)日：2008-04-17
申请号：US11953419
申请日：2007-12-10
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.

8. 发明申请

US20060248481A1 Method and system for reversing the effects of sequential reparameterization on traces 有权
标题翻译：用于逆转顺序重新参数化对痕迹的影响的方法和系统
公开(公告)号：US20060248481A1
公开(公告)日：2006-11-02
申请号：US11105616
申请日：2005-04-14
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.
摘要翻译：公开了一种用于逆参数化反转效果的方法，系统和计算机程序产品。该方法包括接收原始设计，抽象设计和抽象设计的第一个跟踪。一个或多个条件值通过抽象设计填充到第一个跟踪中，并且转换k阶可满足性检查以获得第二个跟踪。一个或多个计算值被连接到具有一个或多个已建立值的第二个跟踪中的初始门集合到抽象跟踪中的初始设计的生成子集以形成新的跟踪，并且重新参数化的一个或多个效果被反转通过在初始设计中返回新的轨迹。

9. 发明申请

US20060248484A1 Method for preserving constraints during sequential reparameterization 失效
标题翻译：在连续重新参数化过程中保留约束的方法
公开(公告)号：US20060248484A1
公开(公告)日：2006-11-02
申请号：US11105611
申请日：2005-04-14
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut gates, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is constrained to force one or more constraint gates representing the one or more constraints to evaluate to a forced valuation, and one or more dead-end states of the constraints are identified. The inverse of the dead-end states is applied as don't cares to simplify the relation and the simplified relation is synthesized to form a first gate set. An abstracted design is from the first gate set and verification is performed on the abstracted design to generate verification results.
摘要翻译：公开了一种用于保护约束的方法，系统和计算机程序产品。该方法包括接收包括一个或多个目标，一个或多个主要输入，一个或多个约束和一个或多个状态元素的初始设计。计算包括一个或多个切割门的初始设计的切割，以及关于一个或多个主要输入和一个或多个状态元素的可生产到一个或多个切割门的一个或多个值的关系。该关系被限制为强制表示一个或多个约束的一个或多个约束门来评估强制估价，并且识别约束的一个或多个死端状态。应用死端状态的倒数不需要简化关系，并且简化的关系被合成以形成第一门集。抽象设计来自第一个门集，并对抽象设计进行验证，以生成验证结果。

10. 发明申请

US20060248482A1 Method for heuristic preservation of critical inputs during sequential reparameterization 失效
标题翻译：在连续重新参数化过程中启发式保存关键输入的方法
公开(公告)号：US20060248482A1
公开(公告)日：2006-11-02
申请号：US11105617
申请日：2005-04-14
申请人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system, and computer program product for preserving critical inputs is disclosed. The method comprises receiving an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results.
摘要翻译：公开了一种用于保护关键输入的方法，系统和计算机程序产品。该方法包括接收初始设计，其包括不能被消除的一个或多个主要输入，可被消除的一个或多个主要输入，一个或多个目标以及一个或多个状态元素。识别包括一个或多个切割门的所述初始设计的切割，以及根据所述一个或多个主要输入而不能被消除的一个或多个可生产到所述一个或多个切割门的值的关系，所述一个或多个主要可以消除的输入和所述一个或多个状态元素被计算。所述关系被合成以形成栅极集合，并且从所述栅极集合形成抽象设计。对所述抽象设计进行验证以产生验证结果。

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